[SOLVED] Paralleling CMOS inverters (NOT logic gates)

[kathmandu]

I'm using such a circuit as a deadtime generator. I could not rely on the MCU for that; moreover, it's much easier to generate a single PWM signal for a half bridge. By the way, I was using 74ACT14 for generating the deadtime, too.

 

[KlausST]

Hi,

I'm using such a circuit as a deadtime generator.

I don´t understand that.
It creates a delay... and maybe it increases (or creates) deadtime for the rising edge, but it makes things worse on the falling edge.

To create a true deadtime you need to use an AND gate or an OR gate after the delay...for low side and high side.

Klaus

 

[kathmandu]

I'm using these inverter gates as a schmitt trigger opamps thus I'm using a RCD circuit at their inputs. This way, they only introduce a delay for the rising edge (or the falling one, depending on C/D configuration).





Both edges are very sharp at the inverter output. By the way, I'm only using one inverter gate (after the RCD network) for one of those branches, to have complementary outputs.

 

[KlausST]

Hi,

Yes, using different circuits with RDC gives true dead time.
This makes sense now...

Thanks

Klaus

 

[kathmandu]

I have to make some corrections to my previous post (for anyone interested in such a circuit).

It actually works OK in that configuration (using 6 inverter gates) as the RCD network has different topology for each branch (one of the diodes is reversed). This way, one branch has a delayed high-low transition while the other one has a delayed low-high transition. I was finding that picture on a quick search on google and I did not payed much attention (was just an example).

In my implementation, I used the same topology for both RCD circuits (delayed low-high transition) thus I only used one gate after one of the RCD networks to have complementary outputs.

Either way, the circuit is working just fine. Sorry for being inaccurate in my previous messages.