Opamp input voltage above its supply voltage?

Hello,

Is it ok that the LT6220 opamp has voltage on its input pins that is above its supply voltage?, as in the attached schematic.

Its just that the datasheet says on the front page that this is ok, but then in the “absolute max” section it says the maximum input voltage is +/-Vs.
These are contradictory statements.

If it is ok, then how high above the supply voltage are the inputs allowed to go?

LT6220 opamp datasheet:
http://cds.linear.com/docs/en/datasheet/622012fc.pdf

Where does it say on the front page that the Vi can be outside +/-Vs?

As far as I can see it only states that the supply voltage range can be between 2V2 and 12V6.
In the note2 it states that to let the inputs go outside +/-Vs, may cause damage the chip.

I would think that answer yor question about the schematic. There are several special ICs that is made for current shunt monitoring, like the INA139 from TI. https://www.ti.com/lit/ds/symlink/ina139.pdf

third paragraph down , first page, RHS of page,

by the way, he opamp isn't supposed to be working in the schem, these are just conditions that it may see at times, and we wonder if it will be damaged by them

Hi.

It seems not, from the datasheet:
"The LT6220/LT6221/LT6222 have an input and output signal range that covers from the negative power supply to the positive power supply."

But I agree with you, paragraph 3 page 1 says what looks like the confusing opposite, which note 2 seems to back up or not to a degree: "Note 2: The inputs are protected by back-to-back diodes. If the differential input voltage exceeds 1.4V, the input current should be limited to less than 10mA." Maybe meaning 12.6V + 1.4V...

I just understand that bearing in mind the total supply voltage (12.6V), the input - and + signals need to be within a 12V framework, like -5 to +5V, or 0V to +12V, but not -5 to +9V, for example.

The input stage of this device most probably uses junction fets, which like any jfet op amp allows the input common mode range to reach and slightly exceed the positive supply rail. But not by much.

Very often there are protection clamping diodes placed on the inputs, so you can quite easily run either of the inputs up to a very few hundred millivolts beyond the positive rail (as with a current shunt) without any problem.

The trick is to power the chip itself from one side of the shunt, rather than a totally independent voltage source.
Make absolutely sure the input voltage is no more than a few hundred millivolts beyond the positive supply rail, and if in doubt, fit current limiting resistors to both inputs.

The chip is designed to do exactly this job, just make sure that the shunt voltage is kept within reasonable limits, and it will work fine.

You should design it to not exceed the supply rails. This means if you have several options to fix this, including;

1. Reduce the gain to attenuate the input CM voltage below 3.3.
2. Use the higher V+ to power the OA
3. Use an exclusive ground side shunt for Isense.
4. Ensure power sequence up/dn satisfies the Vin,Iin max requirements in spec., already mentioned

I see no contradiction.
.