Opamp -1 and +1 stable

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yefj

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Hello, What is the meaning of gain -1 stable, gain of +1 stable for an opamp as shown below?
Does it somehow says that the input signal to the opamp needs to connect on plus or minus to the opamp so it will be stable?
Thanks.
 

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LvW said:
I rather think that the effect of limited slew rate is caused by saturation
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sounds reasonable. This means the input stage determines the dV/dT of the output stage. Is this always the case?
I´ve always treated them independently.

In the meantime the OP stated he does not need to amplify square waves.

Hopefully he eventually defines some useful requirements.

Klaus
 

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Hello,I just want to learn PCB methods to eliminate undesired phenomena's.
For example in here they say that input capacitance forms a pole.
is there a PCB method to tune the input capacitance to push the problematic pole away?
Thanks.
 

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yefj said:
is there a PCB method to tune the input capacitance to push the problematic pole away
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"Tune" means reduce here. Capacitance of PCB copper elements is Epsilon * Area / distance (plate capacitor equation). -> Reduce trace/pad area of critical net, increase distance to other nets, specifically ground.

After implementing reasonable PCB geometry emphasis should be on the other points mentioned in the quote, reduce feedback network impedance if appropriate or use compensation C.
 

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Every line of the datasheet characteristics has some significance. Learn to understand every parameter.

The common mode input has a capacitance of 2.3 pF (typ.) plus trace capacitance to ground. ~ 3 pF/cm (typ) or as Frank says {epsilon*area/gap}

So 2pF is just about perfect with no ground plane under the trace.


Since the schematic shows Rf = Rin- = 1k is much higher R than Rin+= 50
 

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Hello, So in PCB you recommend me to put an empty C1 footpring to fix the stability?(just in case)
Thanks.
 

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yefj said:
Hello, So in PCB you recommend me to put an empty C1 footpring to fix the stability?(just in case)
Thanks.
Click to expand...
Hi,

Mind: if you put a C into the feedback, then it makes the gain to become close to 0 at high frequencies. (below -1, or below +2)
Thus - chosing a too big capacitor - may cause oscillations.
---> using a series RC is the more "rugged" solution. Where the R keeps gain above -1 (towards -2)

Some application notes - when talking about OPAMP stability - use the phrase "Noise gain".
This is the positive gain only - even if using an inverting OPAMP circuit.
It helped me to understand why - for stability - the gain "-1" is identical to gain "+2".


Klaus
 

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KlausST said:
Thus - chosing a too big capacitor - may cause oscillations.
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I think that such a danger does not exist.
The larger the feedback capacitor, the lower the "cross-over frequency" (with unity closed-loop gain) - and the smaller the probability that the additional opamp induced phase shift will lead to instabilities. Typical example: Miller intergator.
 

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LvW said:
The larger the feedback capacitor, the lower the "cross-over frequency" (with unity closed-loop gain) -
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Yes, and here is where I see the problem .. with unity gain loop gain.
--> LT1028 is NOT unity gain stable.
(LT1128 is unity gain stable)

Klaus
 

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The idea is to use a small Cf value that compensates OP-input and trace capacitance, not a "big capacitor".
 

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FvM said:
The idea is to use a small Cf value that compensates OP-input and trace capacitance, not a "big capacitor".
Click to expand...
I fully agree.
That´s what I want to point out. The circuit is good for capacitors in the pF range but may cause problems with capacitors in the nF range and bigger.

I once used a similar configuration. First used the capacitor for stabilisation ... then later had the bad idea to use a bigger capacitor as low pass filter. Didn´t work well.

Klaus
 

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Hello, I want to investigate the stability of non inverting configuration, In the closed loop I
got this spike on the end .
In the loop gain simulation i get something very odd .
did i do the loop gain correctly?
how do i see if i can fix the spike on the end using the loop gain?
Thanks.






 

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1) Closed loop: The "spike" in the region of the pole frequency is called "frequency peaking". It is an indication for a phase margin that could be app. 30 deg.
(for a second-order response there is a fixed and known relationship between phase margin and gain peaking).
This value should be confirmed in the loop gain diagram.

2) Loop gain: Why do you think it would be "very odd"? What did you expect ?
To me, it looks quite normal - the maximum loop gain is app. (150-14)=135 dB at very low frequencies.
And the phase at the frequency where the gain is 0dB confirms the phase margin reading from the closed-loop gain.

So - everything OK.
 
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Although I have never designed a Yig servo, I have analyzed and tested dozens of other servos found in very fast HDD rotary and linear servos with > 10kHz BW.

I suggest you stop considering the LT1x28 models for your servo design. This part is preferred when you can ensure there is no spectral input in the peaking zone of concern. Since the servo design includes the disturbance of a reactive LC load, you will want the maximum gain and phase margin possible in a closed loop to lower the driver impedance. For other applications like a 75 ohm video driver or any high GBW application with a resistive load it is good. Another way to look at this is the Damping Factor DF(f) = Z(load)/Z(source) which is worse case at unity gain f. This is used at the other end of the spectrum for subwoofers in order to combat the back EMF of the coil and therefore have a current force that matches the input signal. Good subwoofer power amps have a DF > 100 which changes with rated impedance 4, 8, 16. Since it is moving the inductive part is loaded by the air resistance back pressure. In your case there is no moving part but there is cable and parasitic C. Thus give up on the LT1028/LT1128. You could use the "overdamping port" which is not modeled but by experimental testing only. But there are alternatives that are more than 10x more BW and stable at the compromise of noise BW which is tiny compared to your other error sources like peaking error.

The std. definition of "stable" does not mean either "maximally flat frequency response" or "critically damped".
It seems these "parameters" are important for you to not degrade your servo performance.

When there is a pole from input capacitance Rs*Cin then a matched feedback zero Rf*Cf with a small Cf is required to reduce peaking at the compromise of GBW. Therefore your selection criteria or "Design Spec" needs to include this.

You have a current source which ideally has infinite impedance in your passband.

If a load capacitance dominates the high impedance of the current source in your spectrum with an inductive load, you must expect voltage resonance.

I think you must place the source directly near the YIG coil and not via a 100 pF/m coaxial cable. Since the spectrum time delay is far less than the cable delay, controlled impedance design rules are irrelevant and it is all about eliminating lumped capacitance on the input and output and external disturbances.

 
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Hello Dana, this method is very good for closed loop system testing.
So every peak is apotentail problem or just the first one?
the first pick is ok 1dB is 50 degree phase margin.
the second peak shown below is a problem too?
Thanks.

 

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Yes, each peak is reflective of a pole, each pole contributes to phase shift (lag).
Notice how steep the phase change with frequency occurs because of this.

Regards, Dana.
 

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Hello Dana, the second pole is due to the last stage i think.
when i changed LT1128 with ad8034 in the last stage i got the bump much smaller as shown in the first photo.
So by changing the opamp and the bump on the second pole became smaller i got the stability better at this point?
Correct?
Thanks.





 

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