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Opamp -1 and +1 stable

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yefj

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Hello, What is the meaning of gain -1 stable, gain of +1 stable for an opamp as shown below?
Does it somehow says that the input signal to the opamp needs to connect on plus or minus to the opamp so it will be stable?
Thanks.
 
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yefj said:
Hello, What is the meaning of gain -1 stable, gain of +1 stable for an opamp as shown below?
Does it somehow says that the input signal to the opamp needs to connect on plus or minus to the opamp so it will be stable?
Thanks.
Click to expand...
The answer to your question was given already in post#10:
"Both cases represent the most critical application as far as stability is concerned (maximum feedback)."

That means: An opamp that is stable for closed-loop gain values of "+1" resp. "-1" wil also be stable for all other gain values (resistive feedback)-
 
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Hello,i have made two types of opamps connected in series as shown below.
In ac sweep its all good, but in step responce i get nothing related to the square shape in the output.
LTSPICE files are attached.
Where did i go wrong in stabilizing the situation when connecting these two?
Thanks.

1708168815853.png


1708168836090.png


1708168862228.png

1708168881780.png
 

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  • LT_spicefiles.rar
    1.4 KB · Views: 69
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The slew rate of LT1028 is worst case 11V / uS.

Your ~ 4V swing, for a sinewave, 250 Khz, would be limited to ~ 4.4 V, and thats for a sinewave,
for a square wave you would need significantly more Slew Rate.

When you used probe you on 10X or 1X at probe ?


Regards, Dana.
 
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Hello Dana, for AD8033 i get 80V slew rate and 10n time step.
but this is only a simulation of two amplifiers connected in series without feedback.
However in real life if i understand correctly there could be parasitic feedback from output to input to and create instability.
how in the layout stage we eliminiate the option of parasitic feedback?
Thanks.
1708174277123.png


1708174192009.png
 
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Hello Dana, phase margin is not relevant here unless i have feedback from output of the second stage to the input of the first stage.
Is it possible for such parasitic feedback to happen ? and how can i avoid it?
Thanks.
 
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Hello Dana, what about filter? do you recommend to plug a filter to the output of the second stage to cancel oscillations and noise?
Thanks.
 
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I think you can do this w/o a filter. Do the OpAmps have a eval board design
you can get the docs for from LTC/Analog Devices, check that out.


Regards, Dana.
 
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yefj said:
Hello Dana, what about filter? do you recommend to plug a filter to the output of the second stage to cancel oscillations and noise?
Thanks.
Click to expand...

It´s always best to remove the root cause than to suppress the symptom.

Generally: OPAMPs are NOT made to amplify square waves.
In datasheet you see square wave test, just specify the limit and the behaviour.
High dV/dt not only causes problems with the limited output dV/dt, but it may cause the input stage to saturate. This may result in distorted output because it takes time for a saturated input stateg to come back to normal regulating mode.

My question: Why did you do a square wave test at all?
Or even better: what are the input and output requirements for your application?

Klaus
 
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KlausST said:
High dV/dt not only causes problems with the limited output dV/dt, but it may cause the input stage to saturate.
Click to expand...
Klaus - I rather think that the effect of limited slew rate is caused by saturation of the opamps input stage - until the delayed feedback brings the unit back to linear operation. During this very short time of saturation the input stage acts as a current source which loads the Miller capacitance of the second stage (frequency compensation) and, thus, causes this nearly linear signal slope which allows the definition of the slew rate.
 
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Hello , I need to amplify sine waves only.square wave test is only to test stability in a lab for closed loop system.
Dana in post 24 suggested that my slew rate is not good at LT1028 that why i switched to AD8034 :)

regarding input capacitance which could cause instability pole.
Is there a way to put some tuning mechanism on the layout that could change input capacitance of the opamp and avoiding it from being unstable?
Thanks.


1708186582395.png
 
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I am still confused what your real lumped elements in the external components and what your design requirements should be for BW , overshoot and parasitic oscillations. These should be defined in some Design Spec.

Supplemental observations:

If you want max slew rate in the LT1x28 family, LT1028 Vin+ is preferred, otherwise AD8034 is better than both.

If you have gain >|1,| such as in your driver, the non-inverting input is preferred for step response. Yet they have a preference to add a series R to Vin+ in datasheets low impedance 100% feedback and otherwise RC negative feedback.

1708191700469.png

The LTspice models are unable to model the "overcompensation" pins in LT1x28 family due to complex multiple internal compensation, unlike conventional Op Amp's with single cap 1st order roll-off of GBW. Thus use of plots of overshoot with overcomp C plots must be used. This makes the behaviors in datasheet more complex than conventional 1 pole compensated Op Amps and why many more characteristic plots (than usual) are given to optimize slew rate vs overshoot vs load vs gain vs input polarity.

You can measure phase margin by adding phase delay to feedback to cause oscillation at the threshold of Barkhausen criteria.

The math for BW vs time domain depends on how it is measured.

The breakpoint for an RC = τ = from initial asymptote 63.2% of step input is the passive half-power point frequency
f(-3dB) = 1/(2π*τ)
The breakpoint for a step pulse rise time tR is between 80% from 10% to 90% of an active step output.
f(-3dB) = 0.35/tR
Yet for higher order systems, swept frequency half-power ~-3dB is the std. method to define BW.

Other:
Playing around with an old version, my result is similar to Dana's

1708190540230.png



Keep in mind some rules of thumb apply most accurately to 2nd order systems below VHF spectrum and as can be see inside LT1x28 and above, this is just an approximation.

1708190935694.png
1708191198880.png
 
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yefj said:
Hello , I need to amplify sine waves only.square wave test is only to test stability in a lab for closed loop system.
Dana in post 24 suggested that my slew rate is not good at LT1028 that why i switched to AD8034 :)

regarding input capacitance which could cause instability pole.
Is there a way to put some tuning mechanism on the layout that could change input capacitance of the opamp and avoiding it from being unstable?
Thanks.


View attachment 188729
Click to expand...
But the filter you posted in another thread only looking for 1 Khz BW ? If so your slew rate
is not very challenging, eg. need for very wide band OpAmps.

So what is max P-P sine you want out and max frequency, then calc slew rate needed :

{\displaystyle \mathrm {SR} \geq 2\pi fV_{\mathrm {pk} },}
(Volts/Sec)

Dont forget to convert to V / uS which most datasheets use.


Regards, Dana.
 
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For designs with little or no Cload ( OP seems to indicate with no external loading in sim )
slew rate is governed by internal OpAmp considerations :

1708201739754.png



But to the broader point this covers both internal and external slew considerations :



Regards, Dana.
--- Updated ---

LvW said:
Klaus - I rather think that the effect of limited slew rate is caused by saturation of the opamps input stage - until the delayed feedback brings the unit back to linear operation. During this very short time of saturation the input stage acts as a current source which loads the Miller capacitance of the second stage (frequency compensation) and, thus, causes this nearly linear signal slope which allows the definition of the slew rate.
Click to expand...
A good ap note on internal versus external slew rate considerations. Attached.

Excellent foundation book by Graeme, discusses SR extensively, attached.


Regards, Dana.
 

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  • 00884a.pdf
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  • Burr_Brown_Operational_Amplifiers_Design_and_Applications_1971.pdf
    24.3 MB · Views: 69
Last edited:
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danadakk said:
For designs with little or no Cload ( OP seems to indicate with no external loading in sim )
slew rate is governed by internal OpAmp considerations :




But to the broader point this covers both internal and external slew considerations :



Regards, Dana.
Click to expand...
SR correlates with GBW or BW in 1st order partial integrator compensation types like the 741. in small signal BW or large signal with current limits from internal feedback or ext load.

But SR does not correlate with GBW in the LT1028/1128 which is asymmetrical in current drive/feedback nor is it 1st order RC comp.
1708206190317.png


Whereas the external "over-compensation" is 1st order dominant so GBW and SR do correlate.
1708206131038.png

--- Updated ---

danadakk said:
For designs with little or no Cload ( OP seems to indicate with no external loading in sim )
slew rate is governed by internal OpAmp considerations :

View attachment 188762


But to the broader point this covers both internal and external slew considerations :



Regards, Dana.
--- Updated ---


A good ap note on internal versus external slew rate considerations. Attached.

Excellent foundation book by Graeme, discusses SR extensively, attached.


Regards, Dana.
Click to expand...
That torn jacket on the Graeme OA book brings back memories of the late 70's when we each had 2 shelves worth of NSC handbooks and Graeme's book.

The reason Sr correlates with full power transition rate, ft, is due to full current limit with a large swing at unity gain.
Saturation affects latency but not Sr.
 
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