need your advice about this layout.

[sophiefans]

This is my improved layout. Any advices are appreciated.
Thanks a lot for the reply all of above.

**broken link removed**

 

[sunny0421]

good look,but in my opinion,you'd better use the min rule,your layout watse some space,and what we need is reduce the cost

 

[sengyee88]

Hi sophiefans,

This is a much better artwork compare to previous version.
However, a few comments from me, FYI:
1. You may not need to do guard ring on the whole opamp. Guard ring those sensitive transistor, such as NMOS diff pair is sufficient. Let the guard ring of whole block (if needed) done by people in charge of top-level integration.
2. Not only NMOS, guard ring should be placed to PMOS too. For this particular layout, you may not need to do so, as the PMOS size is very small. For big PMOS, guard ring ensure proper bulk bias and reduces mismatch.
3. If this layout will be reused quite frequently, I still strongly suggest that output pin place on the right. This is because, from top level view, analog signals will always propagate from left to right, or top to bottom or vice versa. It is seldom to have 90 degree bend, unless area limitation.

 

[YESH_23]

in the differential pair routings also should be symmetric
ur routings can be done in a better way still

 

[road_0506]

try to make ur diff pair balance and add more contacts to the inputs...
i hope this image helps...
observe the balanced wiring ang device placement...
avoid also passing other connections thru the opamp...
this may occupy more space but needed when sensitive matching is required...

[/img]

 

[YESH_23]

ya thats correct
the input to gate contacts should be increased.
and also obsorve the routing symmetry even

 

[sophiefans]

Yes, it looks so symmetry & beautiful.
But, could somebody explain that where i should use wide metel wire or where i sould use narrow wire except for current density consideration?

such as :wide metel=small sheet resister&big parasitic capacitance
Is this right? Or some other consideration?

thanks
regards
sphiefans

 

[sengyee88]

You need to use wide metal for:
1. High current density path
2. Low impedance path (especially important for power line and ESD ring/paths).

wide metal gives smaller metal resistance. You have additional parasitic capacitance on wide metal only if something are under the wide metal. If there is nothing under it (which is the case for power lines that I suggest), wider metal does not add any additional parasitic caps.

 

[road_0506]

narrow lines/wires are acceptable for gate connections...

 

[CISSE]

I am also layouting my first circuit.Can the metal cross the ploy?

 

[srieda]

Cant the criss-crossing of in1 and in2 (45°) be changed??!!!
I understand that there is no current flowing into the gates.. but still as a designer i would be very wary of fringe capacitances that such angles induce...

Also is it not a good idea to draw both the diff inputs with the same metal?? The noise implications will be different...

The paths can be matched through different methods..

 

[piao]

now the improved layout looks pretty good, one more commnents for that, please add at least 2 vias/ contacts if there is enough room.

 

[srieda]

still no answer as to why the input lines are crossing at 45°....

 

[manish12]

yes , matel can cross poly .

they are vertically seperated layers

 

[analayout]

hi

metal crossing the poly is not allowed as per my understanding

regards

analyout

 

[dkace]

CISSE what kind of a question is that? Do you have the technology manual or you are just making an exercise?

Normaly, Polysilicone is right on top of the substrate whereas first metal layer is 0.5 to 2 microns higher! That means that in the real world M1 is on the first floor and Poly in on the ground Floor!

I would suggest to check the page with all the metals you are using and that has accurate description of the distance between them . Try to remember that layout is just overlaping masks for injecting different matterials but NOT at the same time and NOT at the same level.

If you have more to ask please do, I would be glad to help - and everyone else in here I presume!
D.

 

[CISSE]

oh,i mean the cross in space,not at the same plane face.

 

[srieda]

hi

metal crossing the poly is not allowed as per my understanding

regards

analyout

WHY ???

 

[seyyah]

offtopic:

How did you create this image/layout?

 

[fixrouter4400]

It is an normal OP AMP with differential input. The schematic lies in the right lower quadrant.

This is my fist layout which has passed DRC. I don't know what do you think about it. Could you tell me the mistakes you have found?

Thanks in advance.
sophiefans.

**broken link removed**

Hi there,

In my point of view if you really need a good matching between your paired transistors you need to add dummies on both sides. also make sure that the substrate contact is not only connected on one side of the transistor, you should surround it with psub ring.

The input lines if its noisy line..makes sure you put them in shielded lines that is connected to gnd and put as much polycontacts as necessarry.

capacitor you can changed the aspect ratio(you can stretch and make it rectangular not square).

Make your Supply and ground line wide...ask your designer how much current do you need to those...and you can compute the VDD/GND width look at the current handling capabilities of each metal in your design rule.

Also take out those two lines passing the transistor wire them out of the active area

I hope this help you.

cheers