Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Need documents about timing recovery and carrier recovery

Thread starter zhl_gs1980
Start date Oct 27, 2005

Status: Not open for further replies.

Oct 27, 2005

#1

Z

zhl_gs1980

Member level 1

Member level 1

who could provide some content about timing recovery and carrier recovery?

ths!

Oct 30, 2005

#2

B

bm.iitkgp

Newbie level 3

Newbie level 3

Re: need help

perhaps these links can help you:

http://bwrc.eecs.berkeley.edu/Research/IC_Design_Flow/Theses/phusted_masters.pdf
**broken link removed**
**broken link removed**

Status: Not open for further replies.

Similar threads

G
FPGA timing, signaling between processes
- Started by gahelton
- Nov 21, 2023
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
S
Timing Issue
- Started by Sarathjaladi
- May 27, 2023
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
C
Seeking Help with VHDL Timing Issue in Arithmetic Operation
- Started by chandra1502
- Aug 29, 2023
- Replies: 8
PLD, SPLD, GAL, CPLD, FPGA Design
P
Implement carrier detection logic in FPGA
- Started by pulkit.vlsi
- Dec 26, 2022
- Replies: 5
PLD, SPLD, GAL, CPLD, FPGA Design
C
need help with verilog coding a morse code to ascii decoder
- Started by combat5
- May 28, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top