vidyaredy
Member level 2
dcm rst_in clkin_ibufg_out vhdl
hi,
u said u r facing issues in ur previous projects which worked very much fine earlier.... Did u come to know wheter any issues with ISE or modelsim... Plz let me know if u have any idea about ISE webpack whether it generates good outputs or not?
Added after 1 hours 19 minutes:
Hi,
Even though I am getting partial output I mean I am not getting LOCKED output, Still I was simulating design bcz my aim is to get the output clock as twice that of input clock... I am getting error as
# ** Fatal: Integer divide (mod) by zero.
# Time: 1000040 ps Iteration: 19 Process: /top_module/u2/dcm_sp_inst/ps_delay_md_p File: C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd
# Fatal error at C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd line 7216
#
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
plz check the Output wave form....If u need I wil upload my codes... I have taken my system clock as 100MHZ and input to DCM as 50MHZ....
How do I fix it????????
Added after 1 minutes:
hi,
u said u r facing issues in ur previous projects which worked very much fine earlier.... Did u come to know wheter any issues with ISE or modelsim... Plz let me know if u have any idea about ISE webpack whether it generates good outputs or not?
Added after 1 hours 19 minutes:
Hi,
Even though I am getting partial output I mean I am not getting LOCKED output, Still I was simulating design bcz my aim is to get the output clock as twice that of input clock... I am getting error as
# ** Fatal: Integer divide (mod) by zero.
# Time: 1000040 ps Iteration: 19 Process: /top_module/u2/dcm_sp_inst/ps_delay_md_p File: C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd
# Fatal error at C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd line 7216
#
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
plz check the Output wave form....If u need I wil upload my codes... I have taken my system clock as 100MHZ and input to DCM as 50MHZ....
How do I fix it????????
Added after 1 minutes: