[SOLVED] Multiple varying delays to signals in VHDL

[arifboy]

I am working on a VHDL code to insert multiple varying delays to signals. I have shown code below and expected waveforms and present waveforms respectively too. How can the code be changed to get desired waveforms?

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Code VHDL - [expand]
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int := conv_integer(pc);
   
    wait until rising_edge(clk);
 
        if (int >= 0 and int <= 500) then  -- alu/j
            load_logic <= '0';
            store_logic <= '0';
            branch_logic <= '0';
            wait for 20 ns; alu_logic <= '1';    
            wait for 20 ns; alu_logic <= '0';
      
    
        elsif (int >= 504 and int <= 600) then --load
            alu_logic <= '0';
            store_logic <= '0';
            branch_logic <= '0';
            wait for 40 ns; load_logic <= '1';   
            wait for 20 ns; load_logic <= '0';
 
        elsif (int >= 604 and int <= 700) then -- store
            alu_logic <= '0';
            load_logic <= '0';
            branch_logic <= '0';
            wait for 60 ns; store_logic <= '1';
            wait for 20 ns; store_logic <= '0';   
 
        else --- br/j  
            alu_logic <= '0';
            load_logic <= '0';
            store_logic <= '0';
            wait for 80 ns; branch_logic <= '1';
            wait for 20 ns; branch_logic <= '0';        
 
        end if;

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[arifboy]

Please show the screenshot.

One can change 40ns to 20ns, 60ns to 40ns and 80ns to 60ns for next 3 signals after first one, but this way although desired waveforms can be achieved, but code is not in harmony with the waveforms. Whatever my code says it should reflect on waveforms, so that reader knows, what will happen at output, just by reading it.

 

[Akanimo]

Give this a try.

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Code VHDL - [expand]
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...
elsif(int>=504 and int<=600) then
    alu_logic <= '0';
    store_logic <= '0';
    branch_logic <= '0';
    load_logic <= transport '1' after 40 ns, '0' after 60 ns;
    wait on pc;
elsif(int>=604 and int<=700) then
...

---

 

[arifboy]

Give this a try.

---

Code VHDL - [expand]
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...
elsif(int>=504 and int<=600) then
    alu_logic <= '0';
    store_logic <= '0';
    branch_logic <= '0';
    load_logic <= transport '1' after 40 ns, '0' after 60 ns;
    wait on pc;
elsif(int>=604 and int<=700) then
...

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This is the problem "wait until rising_edge(clk);". I found a way to use 'rising_edge(clk)' with if block instead, and the extra cycle was gone. Thanks for your help.

 

[FvM]

I found a way to use 'rising_edge(clk)' with if block instead, and the extra cycle was gone.

That's also how synthesizable code is expected to look like, see post #4.

 

[Akanimo]

This is the problem "wait until rising_edge(clk);". I found a way to use 'rising_edge(clk)' with if block instead, and the extra cycle was gone. Thanks for your help.

Great. I have not used "wait until rising_edge(clk);" before and I didn't think of even looking at it since it seemed like the clock was working. Altogether, it was a good engagement. Thank you.