Depends on which noise sources you need to consider:
Both the gate-related flicker noise voltage and the drain-related flicker noise current are minimum in subthreshold mode,
also the gate-related thermal noise voltage is minimum in subthreshold mode,
but the drain-related thermal noise current is maximum in subthreshold mode.
See e.g. David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design" which gives a good overview, theoretical calculations and practical test results on the context between noise (and a lot of other parameters) and the Inversion Coefficient IC, which is a measure for the inversion mode.