Modelling power supply for cadence simulations

[big_fudge98]

Hi all,

I am designing a circuit which will be taped-out soon. So I need to simulate with real sources. I plan to use QFN 100 packaging which would add 10 nH and 3pH.

How can I model the votage source with these parasistics?

 

[frankrose]

These are package parasitics, not source model components. Source is not depending on the package, it should depend on what are you using as a source (LDO,battery,SMPS). And in the package the model contains other elements, like pin capacitance, bond wire resistance, bonding pad capacitance, why the inductance did you highlight?

 

[big_fudge98]

Somebody from the industry suggested that I use the mentioned value of inductance.
If I am taking the source from an external power suppy, how should I model it for Cadence simulations? Would a simple VDC work? Do I have to add any source impedance. If so, typically what value.

 

[dick_freebird]

What do you know about the characteristics of your chip's
"power take"?

Modeling a CMOS op amp would be very different interests
than a POL DC-DC, than a RFIC, than an ADC. Each has
"care-abouts" that impact output attributes, from power
nonidealities, but each "transfer function" and sensitivity
are different.

You might have in addition to the power supply's inductive
nature and output filter, an intermediate common mode choke
whose inductance might dominate, and demand corresponding
bypassing. You might really, really care about ripple in a RF
system that can modulate and make frequency products of.
You might see that the POL DC-DC applies huge square wave
"slugs" where a CMOS op amp is quasi-constant-current,
and needs huge (and high quality) input decoupling / charge
reservoir.

A suggestion is, first feed your part with an ideal source and
see the current waveform. Then "build" your power supply
model based on what you can find for output characteristics
(DC, Bode plot, step-load response) and see what impact.
Then, on to cleaning that up with realistic close-in decoupling
elements, on-PCB power distribution network and so on.

Some parts, you can neglect all that and use rules-of-thumb
as constrained by BOM cost and component realities. SSI logic?
Throw a 1nF cap at it and move on. Others want a whole project
to themself.

 

[frankrose]

Somebody from the industry suggested that I use the mentioned value of inductance.
If I am taking the source from an external power suppy, how should I model it for Cadence simulations? Would a simple VDC work? Do I have to add any source impedance. If so, typically what value.

VDC is ideal, through big part of the the full design phase it is should be enough. However if you know that your supply will be poor from any standpoint or your circuit is too sensitive it is totally recommended to use a model earlier. We cannot suggest good source model without any knowledge what will you want to use. If you know what are the possible type of sources browse for the datasheet of them, draw the simplified circuit of them and check its settling behaviour, simulate its output impdeance, current limiting behaviour, etc. If you use SMPS with high ripple then model its waveform with VPWL source for example, and check how sensitive your design for it. We cannot tell you more without details I think.