eda4you
Full Member level 5
Maybe someone can help me answering the following question!
For instance assuming a differential nmos input stage. Making the Area W*L for each transistor larger as well as the channel lenght, assures a better matchig and (?) a lower input noise. But on the other hand a larger area will be consumed and (?) the cut off frequency will decrease. Are my consideration right?
To sum it up, I don't know how to choose the L for my input stage in a 0.25µ process. Looking at other designs a lenght is choosen about two times the minimum channel lenght. Why???
For instance assuming a differential nmos input stage. Making the Area W*L for each transistor larger as well as the channel lenght, assures a better matchig and (?) a lower input noise. But on the other hand a larger area will be consumed and (?) the cut off frequency will decrease. Are my consideration right?
To sum it up, I don't know how to choose the L for my input stage in a 0.25µ process. Looking at other designs a lenght is choosen about two times the minimum channel lenght. Why???