[Merged] Why it cannot be read by Design Compiler? (reading takes too long/stuck)

[KYLI0418]

Why does this verilog program take so long to read in Design Compiler? (It cannot be read normally for several hours)
(No errors or warning messages)
I have changed many versions but they get the same results.
Can anyone help me? QQ
Thanks!

 

[FvM]

What's the target hardware you are trying to synthesize the code for?

A brief look reveals that the large memory blocks used in your code can't be implemented in actual RAM because you are reading and writing 30 memory locations in the same clock cycle, would require a 60-port RAM. Even the largest available FPGA won't be able to implement the code. No matter in which compilation phase Design Compiler is presently stuck, it won't produce working logic.

I didn't try to understand the codes purpose. Technically, you are probably able to synthesize the intended function by performing memory access sequentially in a state machine.

 

[ThisIsNotSam]

Here is a hint:

reg [7:0] weight_memory_high [0:269311]

This is more than 2 million flip-flops. And you have at least 2 of those.

 

[KYLI0418]

Thank you both, I know where my problem lies.

 

[KYLI0418]

Why does this verilog program take so long to read in Design Compiler? (It cannot be read normally for several hours)
(No errors or warning messages)

I'm sure the read and write operations are not simultaneous. Or am I wrong in my understanding?

Or is because the array inside too large? Maybe I should split it in half or even more?
I try to use the Block RAM, but I'm not sure this is right way to do it.

Can anyone help me?
Thanks!

 

[KlausST]

Hi,

yesterday you asked almost the same question.

Then you've got some replies.

Without any feedback on the replies, issue, or solution...
... you marked the problem as [solved] and wrote:
[Thank you both, I know where my problem lies.]

This is not how a forum works.

Klaus

 

[KYLI0418]

Hi,

yesterday you asked almost the same question.

Then you've got some replies.

Without any feedback on the replies, issue, or solution...
... you marked the problem as [solved] and wrote:
[Thank you both, I know where my problem lies.]

This is not how a forum works.

Klaus

The error encountered by the module before was that the read and write operations simultaneously caused the DC to be unable to read.

Now this is a different module, and I confirmed the issue with read and write operations.

My question is whether the matrix size exceeds the limit and whether the Block RAM is set incorrectly.
Mainly I want to know what else can be modified.

Thank you, sorry for causing trouble.

 

[KlausST]

Hi,

Forum rules say you should not start several threads with identical/similar problem.

I assume it is the same application, same "too long time to compile" ... and even the headline is identical..
So how can a reader destinguish which thread is which?

In my opinion it is just a follow up of the same problem .... thus I recommend to join both threads. So users can see the steps done before.

If you really think this thread has nothing to do with the previous thread ... it´s valid to start a new thread
... but then with a headline that clearly shows in which regard the new thread differes from the previous thread.

Klaus

 

[KYLI0418]

OK, I understand, sorry for the trouble.

 

[FvM]

I merged both threads and removed the "Solved" mark. Obviously the problem isn't solved, respectively the OP doesn't understand the suggested solution.

In a short, the memory array is too large to be implemented in logic cells but it doesn't meet the requirements for RAM inference. It's not primarily the problem of simultaneous read and write.

 

[KYLI0418]

Sorry for causing trouble, I already understand the problem with these two modules. Currently I am trying other ways to implement the function, thank you.

 

[FvM]

I merged both threads and removed the "Solved" mark. Obviously the problem isn't solved, respectively the OP doesn't understand the suggested solution.

In a short, the memory array is too large to be implemented in logic cells but it doesn't meet the requirements for RAM inference. It's not primarily the problem of simultaneous read and write.