Measuring the execution time on FPGA

[doost4]

Hello again.

I've made some changes in my design but still something seems strange to me.





In these two images, I just changed the data depth from 1024 to 512. but in the 0 frame, my values changes. Is it normal?

 

[ThisIsNotSam]

Hello again.

I've made some changes in my design but still something seems strange to me.

View attachment 140888

View attachment 140889

In these two images, I just changed the data depth from 1024 to 512. but in the 0 frame, my values changes. Is it normal?

what is your testbench doing? that's how you define/control the behaviour you want to see in simulation

from the images it is not possible to tell what you are actually measuring.

 

[ads-ee]

what is your testbench doing? that's how you define/control the behaviour you want to see in simulation

from the images it is not possible to tell what you are actually measuring.

That's not from a simulation, those are chipscope captures based on their changing the data depth from 1024 to 512 and the windows displayed in the images.

What you are seeing is samples with different value at a different times.

I suspect you may not understand what an ILA really does. It compares the signals on the ports connected to the ILA to some trigger (the values you expect the ports to have) and then captures all data for every clock cycle after that trigger.

As you didn't specify any trigger value that I can see...

The ILA immediately triggers when run and you get whatever the value is when it starts running (random values, of what I assume is your counter).

I told you exactly how to setup and run the capture, but I think you first need to go through Xilinx's tutorials on chipscope as you don't seem to have the background knowledge in using chipscope.

 

[ThisIsNotSam]

not simulation, right. but the same principle applies: what was the OP expecting to see in the waveform in the first place? which stimuli is he providing to the dut?