cupoftea
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It has nothing to do with leakage current. ESR will limit current. But dV/dt = Ic/C so the smallest value swings the largest. Ic is shared.Hi,
The attached LTspice sim shows a series cap network getting charged up, and then for some reason the bottom cap discharges.
Do you know why?
View attachment 195811
Default Rpar is infinity for LTspice capacitor models. Discharge in this simulation setup is caused by SPICE minimal node conductance gmin as shown in post #4.Electro's leak - LTspice probably assigns so many Meg ohms to a cap if you do not override it. ( control right mouse on the part )