LTspice: Why Capacitor discharges?

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cupoftea

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Hi,
The attached LTspice sim shows a series cap network getting charged up, and then for some reason the bottom cap discharges.
Do you know why?

 

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The simulation setup is unrealistic. Real capacitors have nonzero leakage current.

What you most likely see is SPICE finite node conductance, can be set in configuration parameters.
 
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Model for caps in simulator ideal, so added some leakage.

Q = C x V, V = Q / C.

So Q1 = C1 x V1, Q2 = C2 x V2. Caps in series so same current
flows in each to charge. So total charge in each same....or so I think.

So C1 x V1 = C2 x V2, V1 ~ .46V, V2 ~ 4.54V

So C1 / C 2 = ~ V2 / V1


Regards, Dana.
 
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Thanks, so due to leakage current, the bottom capacitor could well discharge anyway.....if the leakage current of top and bottom caps was a certain value, then the bottom cap could in fact hold its charge. But is this likely in reality?
 

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Presume you realize that the original problem is a simulator issue.

Regarding real capacitor leakage currents, the capacitors keep there initial voltage distribution if conductance is proportional to capacitance, this may be or may be not the case.
--- Updated ---

Late comment to post #3. Voltage seems constant, but only because simulation time is far too short. Asymptotic probe voltage is 2.5 V.
 
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For sure FVM's point that conductance ultimately controls final value V apply.
G of course different for the two caps (most likely due to dielectric area
considerations due to size differences). If there was no leakage then V would
be a f(C1/C2), the ideal case.

But throw into this the non linear leakage behavior with T and V and might as
well throw away SIM to get a usable result. So conclusion is out the window
as to what will happen.

Note I m assuming electrolytics/chemical dielectrics, given the size of the caps.
But then original sim was in the kV applied, so electrolytics ?

Regards, Dana.
 
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cupoftea said:
Hi,
The attached LTspice sim shows a series cap network getting charged up, and then for some reason the bottom cap discharges.
Do you know why?

View attachment 195811
Click to expand...
It has nothing to do with leakage current. ESR will limit current. But dV/dt = Ic/C so the smallest value swings the largest. Ic is shared.

This is normal for the smaller cap to swing the fastest, charging up then discharging.
 
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the smaller cap has all the volts - usually R discharge is fitted across the caps in inverse proportion to the cap size to keep the same ratio as they discharge

in the real world only high quality LMCC's and film foil caps have miniscule leakage.

Electro's leak - LTspice probably assigns so many Meg ohms to a cap if you do not override it. ( control right mouse on the part )
 
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Easy peasy said:
Electro's leak - LTspice probably assigns so many Meg ohms to a cap if you do not override it. ( control right mouse on the part )
Click to expand...
Default Rpar is infinity for LTspice capacitor models. Discharge in this simulation setup is caused by SPICE minimal node conductance gmin as shown in post #4.

As repeatedly stated, the original problem is a simulation artifact, observed in a technically meaningless fictive setup. It's now overlayed by a derived discussion about real capacitor behaviour.
 
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gmin is specified as "Conductivity added to every PN junction to aid convergence." But it has apparently an additional undocumented function of setting a default Rpar for capacitor models. My assumption of default Rpar = infinity is wrong.
Curiously setting Rpar = 0 has the meaning of infinity.
 
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Kind of interesting that gmin is left attached in tran
analysis; my reading of manuals made me think that
it was only applied to DC OP (and maybe at failed
DC sweep steps)?

Something to keep an eye out for, in other "SPICEs"
I guess.
 

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