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LTSpice multiple model definitions error

Lily_Woods

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I have to design an inverter chain buffer that can drive a 1.5 pF load at 1 GHz with rise time and fall timeeach no more than 10% of the time period. Select a technology node of less than 1 um channellength. Establish the tradeoff between number of stages and the total power consumption whenthe input supply has a source resistance of 50 Ω and rise and fall time each of 5% of the timeperiod. For this, I want to choose a model.

I have picked a 90nm model library from here:

however, I keep getting this error. I have even tried including libraries from other sources yet I get the exact same error. Any idea on how to fix this,please?
I have also tried 180nm from here and get the same error:
 

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I think you must find a model that includes it. It is rejecting NMOS as a model from your library. Check your library settings so it can find NMOS....

Read help file page for .OPTIONS which tells you the defaults for defl and defw are both 100 μm.
Then you define scale factors for W= L=

But there are a lot of variables to define a FET, perhaps others have done this before.

see end for VDMOS

a concerned citizen said ... NMOS4 and PMOS4 symbols, otherwise you only get three pins, no bulk. Then you can RClick normally and insert W and L. All of this is in the manual
 
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I think you must find a model that includes it. It is rejecting NMOS as a model from your library. Check your library settings so it can find NMOS....

Read help file page for .OPTIONS which tells you the defaults for defl and defw are both 100 μm.
Then you define scale factors for W= L=

But there are a lot of variables to define a FET, perhaps others have done this before.

see end for VDMOS

a concerned citizen said ... NMOS4 and PMOS4 symbols, otherwise you only get three pins, no bulk. Then you can RClick normally and insert W and L. All of this is in the manual
Thank you so much. I will follow along with it.
 
Some modeling schemes embed a .model call
in a device's subcircuit definition. Others just
reuse a declared model for many instances.
The multi-layer model supports stuff like
Monte Carlo mismatching per device.

However simulators don't all agree on that,
evidently.

There's a patch-command shown in the error
barf. Did you try it? Seems like the simulator is
not real happy about such things.

Maybe look through that "PTM model" (which
could well be complete garbage) for places
where the same .model line is getting re-read
and re-executed, if it's trying to make some more
elaborate naming (device-specificity) then how
does LTSpice handle that - or, maybe you move
to ngspice which may deal better with IC-style
netlisting?

The "PTM files" linked are just plain dumb .model
statements, and have nothing to do with your
90nm circuit. If these fail then your problem is
just too many invocations. So go find them all
and get rid of all but the first (it may just be one
subcircuit calling its embedded model N times).
 
Some modeling schemes embed a .model call
in a device's subcircuit definition. Others just
reuse a declared model for many instances.
The multi-layer model supports stuff like
Monte Carlo mismatching per device.

However simulators don't all agree on that,
evidently.

There's a patch-command shown in the error
barf. Did you try it? Seems like the simulator is
not real happy about such things.

Maybe look through that "PTM model" (which
could well be complete garbage) for places
where the same .model line is getting re-read
and re-executed, if it's trying to make some more
elaborate naming (device-specificity) then how
does LTSpice handle that - or, maybe you move
to ngspice which may deal better with IC-style
netlisting?

The "PTM files" linked are just plain dumb .model
statements, and have nothing to do with your
90nm circuit. If these fail then your problem is
just too many invocations. So go find them all
and get rid of all but the first (it may just be one
subcircuit calling its embedded model N times).
Thank you so much for the help. The only reason I am on LTSpice is because my professor wants us to work on that. Now, as you said about the PTM library files, yes I also think that the problem is not with the simulator but is with the PTM file. I have one question, when we can define the length and width by Rclicking the nmos then what do we include the library for? I don't know, but when searching for tutorial regarding the CMOS design on LTSpice, the only way people design it is by including the library.
 

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L, W, fingers etc. are -arguments- to the "element card"
that declares a device instance.

The include-files deliver the "model card" with its
construction-specific, non-user-definable attributes
that define the other aspects of the device.

Basically you get X, Y, # (or W, L, NF) and the rest
is the foundry's (or here, somebody making up
stuff they hope is reasonable) responsibility.

Maybe post up the actual subcircuit file(s) for
primitive FETs and see if that's "over-declaring"
the same model over and over?
 
As far as I see, Ltspice doesn't know some of the PTM model parameters. Looks like you need to use a different simulator.
 
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