Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Loop Gain Stability - LTSpice

Status
Not open for further replies.
You don't have to worry about the 39° phase margin before zero crossing, your circuit will be stable. To get exact mathematical answer the simulation is the best combined with empircial considerations. This is the engineering way. If you don't write a thesis and don't want to spend time with basic small signal modeling there is no rule you must. Not a disadvantage if you do, but not necessary.

Ok thanks Frank

I think I will build the board and perform some tests. I couldn’t get my own mosfet model working last night (I tried to create an IRF1324.) model.

I also will be adding a filter across the load which will have a cut off frequency of around 1kHz, so I will just check the effect of this before laying the board out.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top