Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

[hobbyiclearner]

Hi,

I am looking for an old book (about 20 years). Will someone have a copy of 'Introduction to CMOS OP-AMPs and Comparators' by Roubik Gregorian. I wanted to have a look at it first.

Thanks,
Hobbyiclearner

 

[dick_freebird]

Try archive.org, there are many textbooks and semiconductor
databooks there scanned in and downloadable in many formats.
The search there works well too; if you don't find what you're
after, you'll probably find something very much like it.

Searching for the literal title and author in Google often leads
me there.

 

[hobbyiclearner]

Thanks. I got a copy elsewhere. I just wanted to know two more things.

#This book written 20 years back would hopefully cover the details of CMOS Op Amp design of that era. Do you by chance know of any book which deals with the topic focusing on modern era CMOS technology in particular. At that time, I suppose, the technology had a minimum resolution of 1 um. Nowadays it is about less than 0.01 um. If you happen to know any such book, pls. inform me.

# Secondly will it be advisable to read such a book directly. I have BTW some idea of basic analog CMOS blocks and op amp designing.

Looking forward to your suggestions.

Thanks and Regards,
Hobbyiclearner

 

[sutapanaki]

Actually, the book came out somewhere in the early 2000's and by that time 0.18umm technology was already a mainstream. I don't think just the fact that the book is old can prevent you from reading and applying the ideas in it.

This being said, for present day technologies and design with them I would recommend looking into the gm/Id methodology for analog design. There was a book on that that was published last year (I think) Authors are Jaspers and Murmann.

 

[hobbyiclearner]

Thanks. Pls. confirm if you were talking of this book: 'Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables'

Regards,
Hobbyiclearner

 

[Kamran1992]

Introduction to CMOS OP-AMPs and Comparators' by Roubik Gregorian

here is what you are looking for
**broken link removed**
found it at Library genesis

 

[sutapanaki]

Thanks. Pls. confirm if you were talking of this book: 'Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables'

Regards,
Hobbyiclearner

Yes, that's the one.

 

[hobbyiclearner]

Thanks. I had 2 final questions pls.

** What is the advantage of using gm/Id designing technique over the conventional technique?
** Is there any name for the conventional designing technique? I am assuming that this newer technique is referred to as 'gm/Id technique'.

Regards,
Hobbyiclearner

 

[Kamran1992]

** What is the advantage of using gm/Id designing technique over the conventional technique?

I assume that you mean gm derivated from the simple Id=0.5uCox(W/L)Vov^2 by the conventional method. well, it was good since short channel mosfets were not around. Short channel MOS showed some other effects that conventional method couldn't be true anymore and formulating all these second-order effects in a simple and easy to use derivation was not possible. in gm/Id method you can plot gm over Id by high precise models. plus the conventional method didn't predict gm and Id in sub-threshold region which is very important in low power design.

** Is there any name for the conventional designing technique? I am assuming that this newer technique is referred to as 'gm/Id technique'.

I don't know, its just based on simple Id equation. gm/Id was introduced first in 1996(So it's not that new). but there is a newer method called Inversion Coefficient introduced in 2015 by "Wiley Sansen" which characterizes MOS in 3 different operating regions(Weak, Moderate and Strong inversion). they are based on how much channel is inverted which gives a good estimation of power consumption, speed and Gm efficiency. This method gives a very good sense of speed-power trade-off.

 

[sutapanaki]

Thanks. I had 2 final questions pls.

** What is the advantage of using gm/Id designing technique over the conventional technique?
** Is there any name for the conventional designing technique? I am assuming that this newer technique is referred to as 'gm/Id technique'.

Regards,
Hobbyiclearner

The traditional square low equations used for hand calculations in designing analog circuits are quite unprecise when it comes to newer technologies, say below 0.18u. gm/Id methodology of designing circuits is meant to avoid that. It is in fact a look up table approach, similar to the ways designers used to design with bipolar transistors. Using the gm/Id method, you use parameters that matter from design point of view. Analog design cares about gm and gm/Id in effect says how much current you invest to achieve the needed gm. Then, gm/Id is used as the main variable and a proxy for the inversion coefficient. gm/Id does not depend on W of the device, at least to 1st order and is inversely proportional to overdrive voltage - in square low speak it is Vov=2/(gm/Id). Another metric is gm/Cgg - how much Cgg a given gm costs. This is close to Ft of the device and relates to the speed of the transistor and the circuits it is used in. Also does not depend to 1st order on W. The third metric is gm/gds or the intrinsic gain of the transistor, not dependent on W. Finally one plots Id/W vs gm/Id and uses it for finding W after knowing gm/Id and Id itself.
Since gm/Id, gm/Cgg, gm/gds and Id/W are plotted from simulations they produce pretty accurate design results, maybe within 10-15% from what circuit simulation shows. Then one can use simulation to hone in to the final result.

 

[timof]

Thanks. I got a copy elsewhere. I just wanted to know two more things.

#This book written 20 years back would hopefully cover the details of CMOS Op Amp design of that era. Do you by chance know of any book which deals with the topic focusing on modern era CMOS technology in particular. At that time, I suppose, the technology had a minimum resolution of 1 um. Nowadays it is about less than 0.01 um. If you happen to know any such book, pls. inform me.

Analog design in advanced nodes (such as 10nm, 7nm, 5nm) is VERY different form older nodes in this sense - layout parasitics in older nodes were second order effect, and devices were playing the primary role.
In advanced nodes, the layout and its parasitics are playing the primary role.
It's a first order effect.
Designs are now layout driven.
Your design is your layout.

People dealing with these advanced nodes learn this truth the hard way, because EDA industry does not help much with this transition.

You won't find any book or even articles describing these issues in detail, mostly because these details contain proprietary foundry information.

In fact, the truth of the matter is, if you do not work with these technologies, you do not need to know this (unless you are really curious).
On the other hand, if you are working with these technologies, you learn these things at work, very often - the hard way (i.e. by spending enormous amount of time, often searching in the dark, to find out some trivial things that are not explained by the foundries upfront, and explained well.)

Max