Re: ESD Architechture
Check out Ming-Dou Ker. He has over 100 patents about ESD across every design
field and he is a consultant all around the world, so his paers and patents are very practical.
I have some experience to share with you about ESD as I have struggled for a year to achieve 8kV HBM in my IO-ring
(1) Check out patents and papers and choose the simplest.
(2) Gate-coupled structure is already good enough to achieve at least HBM 2kV
(3) Check which standard you need, HBM / MM / CDM ? Different standard may require different structure
(4) Modify your simple circuit from some existing papers or patents
(5) Run transient simulation to emulate ESD like pulse. Check the papers from the above guy
(6) Make sure you have more than enough margin to layout. Don't trust the design rules from foundry. Left more margin, like poly gate width, contact-to-gate spacing, min. buffer size, those are very critical from failed 1kV to pass 2kV region
(7) Check out the discharge path for whole chip in layout as the discharge path is critical for your success. Most likely, it is VDD and VSS path.