Logic or sample code to detect the zero crossing Also how detect the positive or negative cycles

[thannara123]

Hi,
Firstly saying this question is the part of desgin of a sinewave inverter by an STM32 controller

A Feed back volt is given to the ADC of the controller after , Scaling and necessory process as said in a previous thread .


Thorugh the internet , most of detecting by " in between the adc values at the zero level of the signal "
like wise
if (adc_value >=1400 && adc_value <=1600){ Zero crossing detected }


Here am reading 400 samples (each conversion takes 25 us) for 10 millisecond one half cycle which is saving to an array[400] by DMA

Hello experts
Here i am requesting the logic or sample code to detect the zero crossing Also how detect the positive or negative cycles

( I am doing this project for learning purpose , Error and accuracy may change it will correct after understanding the basics.And after making a working proto type so this project hasnt any accuracy ,error etc deal binding )

 

[D.A.(Tony)Stewart]

Can you do what I asked? Research it , if not.

 

[doraemon]

Hello!

It looks good (essentially), although I haven't run it to verify if it works.
But why do you use 2 definitions, POSITIVE and POSITIVE_HALF_CYCLE. It looks more or less the same thing.
And the 2 variables you use change exactly under the same conditions, which makes me think that currentstate
is always equal to current_half_cycle. So you can get rid of one of them.
Beside this, be careful, one case is not covered:
In you loop you have if something <, then if something >. What about if something ==?

Dora.

 

[betwixt]

There is yet another alternative method using an ADC in unipolar mode but it only works for regular waveforms (sine, square etc.).
Rectify the input so you only have positive half cycles. Next look for the input going above zero (or some suitably low value if noise is present) and measure the time until the same occurs again. Repeat that process a few times to find the average time period. The samples taken will be very shortly after zero crossing, when the ADC could just measure 'something' was there. Next, delay by one quarter of the measured period, this should coincide with the peak of the positive swing. If the ADC measures a higher voltage then you have found the positive half cycle and the negative peak will be half a period later.

No method is perfect in the presence of noise and I don't imply the method above is better, it's just an alternative idea based on the symmetry of the waveform.

Brian.

 

[D.A.(Tony)Stewart]

Merry Xmas from Canada.

Unipolar math works too if Vref is subtracted. You can measure over whole cycle but comparing half cycles checks for DC offset error or noise or hysteresis causes. when these errors are simulated and eliminated, whole cycle is ideal for avg. power when current is asymmetrical.

When delta V change =0 it may be zero crossing and maybe is locked with timer for sample interval. (FLL & PLL) depends on history or events.

 

[thannara123]

Thanks for the replays ,
I want to know, can i use a PLL for for my signal which issaved in the array after detecting the Zero crossing .
ie, firstly readtheadc samples for thechalf cycles
after detecting the zero crossing the AD_DMA will restart ,It will store the data from zero th position so the complete array will be one half cycle.
Can i use here a Phase Locked Loop ?
i didnt used any PLL .
sorry if the question is nonsense

 

[betwixt]

Merry Christmas from Wales.

Similar to my previous suggestion but without rectification - the zero crossing will be half way between the points of inflection on the waveform. If you repeatedly sample until the ADC value changes direction to find the peak and trough, measure the period and ZC is half that period afterwards.
Brian.

 

[D.A.(Tony)Stewart]

If this PLL responds to the XOR ZCS pulse on IRQ and has the N sample cycle counter-end matching with 1/2 or full cycle to be locked in sync within 1 count. Then Lock bit can be set and the result ought to be accurate locked to f and phase. (FLL & PLL). There are other ways but involve start-stop pointers in an array.

 

[thannara123]

If this PLL responds to the XOR ZCS pulse on IRQ and has the N sample cycle counter-end matching with 1/2 or full cycle to be locked in sync within 1 count. Then Lock bit can be set and the result ought to be accurate locked to f and phase. (FLL & PLL). There are other ways but involve start-stop pointers in an array.

Sorry sir
I am not able to understand what it is , I am hardly trying to understand it ?

 

[D.A.(Tony)Stewart]

Get Zero Crossing from square wave
Wait for it (IRQ) while using timer/counter estimate number N saved for ADC samples before next IRQ event. ( this N sample is the the timer interval to compute frequency and when it matches the previous N, you must be locked onto f and phase (FLL- frequency locked loop and PLL)

You must have a stack of processes you need to do and try to fit them in during DMA from ADC or after.

If you don't understand, get google to translate.

 

[FvM]

[Please ignore this post] It seems like original question and follow-up questions by thread starter thannara123 have been deleted or otherwise disappeared. The same happened with the similar topic predecessor thread. I wasn't aware that it's even possible to delete the start-up post after several days.

 

[thannara123]

It seems like original question and follow-up questions by thread starter thannara123 have been deleted or otherwise disappeared. The same happened with the similar topic predecessor thread. I wasn't aware that it's even possible to delete the start-up post after several days.

Sir ,i didn't deleted any post .
Is there any option to delete the post which have published ?
I am wondering sir

 

[FvM]

Sorry for the confusion. Everything o.k. with your thread. I inadvertently pressed an ignore button and your posts disappeared for me. Just my fault.