logic of fixing biasing misselighnment

[yefj]

Hello ,In the video at 6:49 they say that the biasing is not alighed and we need to fix it.
Looking in the diagram of the attached photo,where is the misalighnment we need to fix using feedback?
Thanks.

 

[ahsrabrifat]

When the video says the "biasing is not aligned" at 6:49, it usually means that:

• The DC operating point (bias voltage or current) of the circuit is off.
• Without correction, the output of the amplifier or active device (like a transistor or op-amp) will not be centred properly within the desired range.
• This could cause clipping, nonlinear operation, or incorrect amplification.

 

[dick_freebird]

I think it refers to the asymmetric impedance seen
by the right-hand example, which with Iib creates
two different @-pin voltages and adds to the
observed Vio (to be gained up).

 

[yefj]

Hello,I have built a circuit presented below.
How can I create a common mode missalighnment which I could fix later using feedback?
Ltspice file is attached.
Thanks.

--- Updated Yesterday at 6:38 PM ---

update2:

I have created a misselighment by changing mosfet W and I connected the V3 as independant source.
How feedback will fix this misselighnment?

 

[dick_freebird]

Just declare Vcm target to be other than its natural-@-null voltage, and have yourself a time.

 

[yefj]

Hello,what is the phrase below mean?
"natural-@-null voltage, and have yourself a time"
Thanks.

--- Updated Yesterday at 7:13 PM ---

update:
how does increasing te gape pmos vltage fixes the difference between Vop and Vom?(in the photo below)
Thanks.

 

[D.A.(Tony)Stewart]

Dick said to null the differential input to get your Vcm outputs and choose an appropriate Vcm input to offset things.

Vcm out are your FET drains which is the average = (Vop/2+Von/2) .
That is usually defined by Vref= Vcm = Vdd/2 on Vin- above.
That results in a bias Vb that controls the Pch gates to control the current to achieve that mean or common-mode voltage for a given tail current of Io.

So anything changes like the FET gm, Vt, Vcm, and Io then the Op Amp will adjust the Vb to control the mean drain voltages.
(now you know how to create an offset)

Since the drain inverts the gate control, the Op Amp inputs are swapped for negative feedback.

Normally Vcm = Vdd/2 but if Vdd is very low, you will compute a better formula to maximize drain swing without distortion.

Look at what happens when you control Vcm input and keep the Op Amp Vref fixed and measure the Vcm input range for a small linear diff. signal.

Does it behave like a CMOS Op Amp rail to rail? no.
Does the Vcm input reach Vdd?