LNA circuit not working

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promach

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I am trying to simulate a LNA circuit from the book "Design of CMOS RF Integrated Circuits and Systems"

However, it is still not working. Any help ?





mosfet_018.lib

Code: 
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM


*-----------------------------------------------------------------------
.subckt NM D G S B 
+params: W=10u L=1u
M1 D G S B NM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}
.ends

* ----------------------------------------------------------------------
* NMOS transistor model 
* ----------------------------------------------------------------------
.MODEL NM NMOS LEVEL=49
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format    : LTspice
* model     : MOS BSIM3v3
* ----------------------------------------------------------------------
*                        TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
+VERSION = 3.1            TNOM    = 27             TOX     = 4.1E-9
+XJ      = 1E-7           NCH     = 2.3549E17      VTH0    = 0.354505
+K1      = 0.5733393      K2      = 3.177172E-3    K3      = 27.3563303
+K3B     = -10            W0      = 2.341477E-5    NLX     = 1.906617E-7
+DVT0W   = 0              DVT1W   = 0              DVT2W   = 0
+DVT0    = 1.6751718      DVT1    = 0.4282625      DVT2    = 0.036004
+U0      = 327.3736992    UA      = -4.52726E-11   UB      = 4.46532E-19
+UC      = -4.74051E-11   VSAT    = 8.785346E4     A0      = 1.6897405
+AGS     = 0.2908676      B0      = -8.224961E-9   B1      = -1E-7
+KETA    = 0.021238       A1      = 8.00349E-4     A2      = 1
+RDSW    = 105            PRWG    = 0.5            PRWB    = -0.2
+WR      = 1              WINT    = 5e-9              LINT    = 2.351737E-8
+DWG     = 1.610448E-9
+DWB     = -5.108595E-9   VOFF    = -0.0652968     NFACTOR = 2.4901845
+CIT     = 0              CDSC    = 2.4E-4         CDSCD   = 0
+CDSCB   = 0              ETA0    = 0.0231564      ETAB    = -0.058499
+DSUB    = 0.9467118      PCLM    = 0.8512348      PDIBLC1 = 0.0929526
+PDIBLC2 = 0.01           PDIBLCB = -0.1           DROUT   = 0.5224026
+PSCBE1  = 7.979323E10    PSCBE2  = 1.522921E-9    PVAG    = 0.01
+DELTA   = 0.01           RSH     = 6.8            MOBMOD  = 1
+PRT     = 0              UTE     = -1.5           KT1     = -0.11
+KT1L    = 0              KT2     = 0.022          UA1     = 4.31E-9
+UB1     = -7.61E-18      UC1     = -5.6E-11       AT      = 3.3E4
+WL      = 0              WLN     = 1              WW      = 0
+WWN     = 1              WWL     = 0              LL      = 0
+LLN     = 1              LW      = 0              LWN     = 1
+LWL     = 0              CAPMOD  = 2              XPART   = 0.5
+CGDO    = 7.7E-10        CGSO    = 7.7E-10        CGBO    = 1E-12
+CJ      = 1.010083E-3    PB      = 0.7344298      MJ      = 0.3565066
+CJSW    = 2.441707E-10   PBSW    = 0.8005503      MJSW    = 0.1327842
+CJSWG   = 3.3E-10        PBSWG   = 0.8005503      MJSWG   = 0.1327842
+CF      = 0              PVTH0   = 1.307195E-3    PRDSW   = -5
+PK2     = -1.022757E-3   WKETA   = -4.466285E-4   LKETA   = -9.715157E-3
+PU0     = 12.2704847     PUA     = 4.421816E-11   PUB     = 0
+PVSAT   = 1.707461E3     PETA0   = 1E-4           PKETA   = 2.348777E-3     



*-----------------------------------------------------------------------
.subckt PM D G S B 
+params: W=10u L=1u
M1 D G S B PM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}
.ends

* ----------------------------------------------------------------------
* PMOS transistor model 
* ----------------------------------------------------------------------
.MODEL PM PMOS LEVEL=49
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format    : LTSPICE
* model     : MOS BSIM3v3
* ----------------------------------------------------------------------
*                        TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
+VERSION = 3.1            TNOM    = 27             TOX     = 4.1E-9
+XJ      = 1E-7           NCH     = 4.1589E17      VTH0    = -0.4120614
+K1      = 0.5590154      K2      = 0.0353896      K3      = 0
+K3B     = 7.3774572      W0      = 1E-6           NLX     = 1.103367E-7
+DVT0W   = 0              DVT1W   = 0              DVT2W   = 0
+DVT0    = 0.4301522      DVT1    = 0.2156888      DVT2    = 0.1
+U0      = 128.7704538    UA      = 1.908676E-9    UB      = 1.686179E-21
+UC      = -9.31329E-11   VSAT    = 1.658944E5     A0      = 1.6076505
+AGS     = 0.3740519      B0      = 1.711294E-6    B1      = 4.946873E-6
+KETA    = 0.0210951      A1      = 0.0244939      A2      = 1
+RDSW    = 127.0442882    PRWG    = 0.5            PRWB    = -0.5
+WR      = 1              WINT    = 5.928484E-10   LINT    = 3.468805E-8
+DWG     = -2.453074E-8
+DWB     = 6.408778E-9    VOFF    = -0.0974174     NFACTOR = 1.9740447
+CIT     = 0              CDSC    = 2.4E-4         CDSCD   = 0
+CDSCB   = 0              ETA0    = 0.1847491      ETAB    = -0.2531172
+DSUB    = 1.5            PCLM    = 4.8842961      PDIBLC1 = 0.0156227
+PDIBLC2 = 0.1            PDIBLCB = -1E-3          DROUT   = 0
+PSCBE1  = 1.733878E9     PSCBE2  = 5.002842E-10   PVAG    = 15
+DELTA   = 0.01           RSH     = 7.7            MOBMOD  = 1
+PRT     = 0              UTE     = -1.5           KT1     = -0.11
+KT1L    = 0              KT2     = 0.022          UA1     = 4.31E-9
+UB1     = -7.61E-18      UC1     = -5.6E-11       AT      = 3.3E4
+WL      = 0              WLN     = 1              WW      = 0
+WWN     = 1              WWL     = 0              LL      = 0
+LLN     = 1              LW      = 0              LWN     = 1
+LWL     = 0              CAPMOD  = 2              XPART   = 0.5
+CGDO    = 7.11E-10       CGSO    = 7.11E-10       CGBO    = 1E-12
+CJ      = 1.179334E-3    PB      = 0.8545261      MJ      = 0.4117753
+CJSW    = 2.215877E-10   PBSW    = 0.6162997      MJSW    = 0.2678074
+CJSWG   = 4.22E-10       PBSWG   = 0.6162997      MJSWG   = 0.2678074
+CF      = 0              PVTH0   = 2.283319E-3    PRDSW   = 5.6431992
+PK2     = 2.813503E-3    WKETA   = 2.438158E-3    LKETA   = -0.0116078
+PU0     = -2.2514581     PUA     = -7.62392E-11   PUB     = 4.502298E-24
+PVSAT   = -50            PETA0   = 1E-4           PKETA   = -1.047892E-4 
* ----------------------------------------------------------------------

LNA1.asc

Code: 
Version 4
SHEET 1 944 852
WIRE 144 80 0 80
WIRE 256 80 144 80
WIRE 368 80 256 80
WIRE 480 80 368 80
WIRE 592 80 480 80
WIRE 0 128 0 80
WIRE 144 144 144 80
WIRE 480 144 480 80
WIRE 592 144 592 80
WIRE 0 240 0 192
WIRE 480 272 480 224
WIRE 592 272 592 208
WIRE 592 272 480 272
WIRE 688 272 592 272
WIRE 800 272 752 272
WIRE 144 288 144 224
WIRE 480 320 480 272
WIRE 544 368 480 368
WIRE 368 400 368 80
WIRE 432 400 368 400
WIRE 80 448 80 400
WIRE 480 448 480 416
WIRE 704 448 480 448
WIRE 480 480 480 448
WIRE 240 512 160 512
WIRE 384 512 304 512
WIRE 544 528 480 528
WIRE 704 528 704 448
WIRE 384 560 384 512
WIRE 432 560 384 560
WIRE -128 576 -192 576
WIRE 80 576 80 528
WIRE 80 576 -64 576
WIRE 160 576 160 512
WIRE 160 576 80 576
WIRE 480 592 480 576
WIRE 544 592 544 528
WIRE 544 592 480 592
WIRE 160 656 160 576
WIRE 240 656 160 656
WIRE 384 656 384 560
WIRE 384 656 320 656
WIRE 480 672 480 592
WIRE 704 672 704 592
WIRE -192 688 -192 576
WIRE -192 832 -192 768
FLAG 0 240 0
FLAG 480 672 0
FLAG 704 672 0
FLAG 544 368 0
FLAG 800 272 RF_out
FLAG -192 576 RF_in
FLAG -192 832 0
FLAG 144 288 0
FLAG 80 400 Vdd
FLAG 256 80 Vdd
SYMBOL nmos4 432 480 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M1
SYMATTR Value NM
SYMATTR Value2 L=2u W=0.18u
SYMBOL nmos4 432 320 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M2
SYMATTR Value NM
SYMATTR Value2 L=2u W=0.18u
SYMBOL cap 304 496 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 3p
SYMBOL cap 576 144 R0
SYMATTR InstName Cd
SYMATTR Value 5p
SYMBOL ind 496 128 M0
SYMATTR InstName Ld
SYMATTR Value 1n
SYMBOL ind 224 640 M90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 1n
SYMBOL ind 96 544 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Lbias
SYMATTR Value 1n
SYMBOL cap -64 560 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cin
SYMATTR Value 1p
SYMBOL cap 16 192 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName Ca
SYMATTR Value 1�
SYMBOL cap 752 256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cout
SYMATTR Value 1p
SYMBOL cap 688 528 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL voltage 144 128 R0
SYMATTR InstName Vsupply
SYMATTR Value DC 1.8
SYMBOL voltage -192 672 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(1.8 10u 1G 1n)
TEXT 56 0 Left 2 !.lib mosfet_018.lib
TEXT 400 8 Left 2 !.tran 100n
 

XC3=7 Ohm@2.25GHz at the Drain of M3 !
You cannot get any Gain from this stage..I don't know about operating point of MOS transistors..
 

You are using 1GHz input, and a 2.2GHz resonant LC tank. Hmm... what could be the problem? And yes, C3 makes no sense, 16Ohm at 1GHz, Lbias is like 6Ohm, W of your devices is too small, L is too big, biasing is probably not suitable to keep devices in a normal operating region.
 

Tank Circuit resonates at 2.25GHz but you drive the circuit with 1GHz.. No gain, no pain..
 

I have modified the circuit accordingly, but the LNA circuit still does not give POSITIVE GAIN

 

How did you arrive at the component values?

And why don't you utilize the simulation tool to get the information it can give? It's easy to determine that the signal is already lost in the dubious input LC circuit.
 
@FvM

Thanks for the LC high pass tips. I have corrected the value of Cin.

However, the voltage gain is still negative.

 

promach said:
I have modified the circuit accordingly, but the LNA circuit still does not give POSITIVE GAIN

Click to expand...

These are the issues I can see with your circuit..
1. That Lbias value of 1nH is quiet low. And anyway your sinevoltage source has a DC value of 1.8V. Do you still need that biasing circuit in this?
2. The input LC tank will give you a resonant frequency of 2.9058 GHz
3. You are biasing your CS stage with a Vgs of 1.8V and your cascode gate voltage is also 1.8V. I doubt if M1 will be in saturation (No saturation == low gain)
 

@vivekroy

See post #7 instead for the updated circuit
 

Also for the updated circuit, it's quite easy to see why it has no output, although the situations is different from the previous one. The unclear point is, what make you think it should have significant gain with the given dimensioning?
 

Lbias=1nH .It's too low..
SUB of M2 i connected to GND. It should be connected to SOURCE otherwise Vth will be higher.
 

I have already increased the dimension for M1, thus making M1 operating in saturation region.

However, I am still getting negative gain for the LNA circuit.

Could anyone else advise ?
 

I just saw the mistake in your figure.. You have a w=0.18u and l=6u!!!! Good luck getting a gain out of that!!!

Anyway, I am on vacations and I was getting bored..

So I took your circuit, got rid of your biasing network and I was able to get a gain >0.

So its clearly possible. Size up the devices for more gain.


 

See the following LNA circuit with positive gain.

However, I am bit concerned with the values of Cin and C3.

Their values seem to affect the gain a lot



LNA1.asc

Code: 
Version 4
SHEET 1 944 852
WIRE 144 80 0 80
WIRE 256 80 144 80
WIRE 368 80 256 80
WIRE 480 80 368 80
WIRE 592 80 480 80
WIRE 0 128 0 80
WIRE 144 144 144 80
WIRE 480 144 480 80
WIRE 592 144 592 80
WIRE 0 240 0 192
WIRE 480 272 480 224
WIRE 592 272 592 208
WIRE 592 272 480 272
WIRE 688 272 592 272
WIRE 800 272 752 272
WIRE 144 288 144 224
WIRE 80 304 -192 304
WIRE 480 320 480 272
WIRE -192 352 -192 304
WIRE 544 368 480 368
WIRE 368 400 368 80
WIRE 432 400 368 400
WIRE 80 448 80 304
WIRE 480 448 480 416
WIRE 816 448 480 448
WIRE -192 480 -192 432
WIRE 480 480 480 448
WIRE 240 512 160 512
WIRE 384 512 304 512
WIRE 544 528 480 528
WIRE 816 528 816 448
WIRE 384 560 384 512
WIRE 432 560 384 560
WIRE -96 576 -192 576
WIRE 80 576 80 528
WIRE 80 576 -32 576
WIRE 160 576 160 512
WIRE 160 576 80 576
WIRE 480 592 480 576
WIRE 544 592 544 528
WIRE 544 592 480 592
WIRE 160 656 160 576
WIRE 240 656 160 656
WIRE 384 656 384 560
WIRE 384 656 320 656
WIRE 480 672 480 592
WIRE 816 672 816 592
WIRE -192 688 -192 576
WIRE -192 832 -192 768
FLAG 0 240 0
FLAG 480 672 0
FLAG 816 672 0
FLAG 544 368 0
FLAG 800 272 RF_out
FLAG -192 576 RF_in
FLAG -192 832 0
FLAG 144 288 0
FLAG 256 80 Vdd
FLAG 816 448 M1_drain
FLAG 592 272 M2_drain
FLAG -192 480 0
SYMBOL nmos4 432 480 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M1
SYMATTR Value NM
SYMATTR Value2 L=150u W=0.18u
SYMBOL nmos4 432 320 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M2
SYMATTR Value NM
SYMATTR Value2 L=150u W=0.18u
SYMBOL cap 304 496 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 3p
SYMBOL cap 576 144 R0
SYMATTR InstName Cd
SYMATTR Value 5p
SYMBOL ind 496 128 M0
SYMATTR InstName Ld
SYMATTR Value 1n
SYMBOL ind 224 640 M90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 1n
SYMBOL ind 96 544 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Lbias
SYMATTR Value 1n
SYMBOL cap -32 560 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cin
SYMATTR Value 6p
SYMBOL cap 16 192 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName Ca
SYMATTR Value 1�
SYMBOL cap 752 256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cout
SYMATTR Value 1p
SYMBOL cap 800 528 R0
SYMATTR InstName C3
SYMATTR Value 0.1p
SYMBOL voltage 144 128 R0
SYMATTR InstName Vsupply
SYMATTR Value DC 3.3
SYMBOL voltage -192 672 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(1.8 10u 2.25G 1n)
SYMBOL voltage -192 336 R0
SYMATTR InstName DC_bias
SYMATTR Value DC 2.5
TEXT 56 0 Left 2 !.lib mosfet_018.lib
TEXT 400 8 Left 2 !.tran 50n
 

Are you sure you need a length of 150u and a width of 0.18u?
 

Yes, for a positive gain.

What is typical gain for a LNA ?
 

promach said:
Yes, for a positive gain.

What is typical gain for a LNA ?
Click to expand...

Where did you hear about that high L generates positive gain? Gm will decrease with higher L, parasitics will increase.
Why don't you run AC analysis rather to get information about gain?
 

Adding series input impedance (Rs) and the shunt output load impedance (RL) just made things worse. Now, I have negative gain.

It seems like I am dealing with impedance matching issue here.

 

You have nanoamper operating drain current. You are far from matching problems. Simply your bandwidth is much lower than the LC resonance frequency. Nobody ever designed a GHz amplifier with nA or even uA current consumption. Go up to mA-s.
 
@frankrose

I have increased the Id to mA , yet the LNA circuit still give negative gain

 

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