Links for a Design of a 6 transistor SRAM

[Pragati Rana]

Re: Help needed in design of a 6 transistor SRAM

Current information in hspice simulation can be read directly by awaves program.

i have a project on 6t sram.
i am a beginner in hspice as well as sram.\please help with all possible useful links

 

[dick_freebird]

Re: Help needed in design of a 6 transistor SRAM

The SRAM designs I've seen, which are pretty old now,
used a column precharge and the bit cell would discharge
it, or not, when connected. This made the operation low
power, but the capacitance needed to be less than would
upset the bit when attached by the switch (or, core pair
sized up to accommodate the line capacitance). I doubt
anyone wants a DC load on a read line so this scheme may
still dominate. In which case, your schematic needs to
represent a somewhat realistic C on the true and complement
lines.

Your sense amp might simply be a cross-coupled inverter pair
that is attached across those lines, and the charge difference
on the true / complement Cs will be regeneratively gained up
to a logic level. This needs to be synchronized, the precharge
and the sense amp and the latching of result, a mini state
machine. You don't want precharge to be any longer than
necessary, since it's a slug of power wasted into the sense
amp, but long enough to charge Cline (varying w/ layout,
processing, temp, Vdd, etc.).

 

[Pragati Rana]

Re: Help needed in design of a 6 transistor SRAM

thank u dick. but would be glad if u could help me with the basics.
i need to design a 6t sram for my project in hspice.
i need the code.
how can i proceed??

 

[the_pro]

Re: sram write precharge schematic -patent -ieee

Please be informed that,
you may design SRAM with 6T by refering any reference book, but testing/simulation for write/read/idle cycle of SRAM is not that easy as we expected, for that you are required additional circuits to be attached together with 6T SRAM. Those additional circuits are precharge circuit (4T),sense amplifier (4T), and equalizer(1T) and 2 chargeing capacitors.

hi....
i have implemented SRAM design in LTspice.
i have not included this two capacitor .....
what is the purpose of this two capacitor ?
why it is required ?