Sort of, in the sense that you move the usable range of
current-source (sink) common mode voltage up to
(Vs2+VT)
Vs2+BVdss) at the drain of the "level shifter"
from (Vs1+VT)
Vs1+BVdss) at the drain of the "current
mirror". Subject of course to other realities like Vgb, Vdb
limits in junction isolated technologies.
But often the use of this topology-nugget is not about
gaining a higher working voltage position, but controlling
the Vds swing of the current mirror to attain best match,
best PSRR, etc. Seldom is level shifting the primary goal,
in analog amplifier design, and you will see this form used
where no such gross level shifting is needed (although I
have also done some pretty tall stacks in low voltage SOI
that were all about the level shift, or more appropriately
the safe / reliable partitioning of working voltage).