LDO PSRR shape is not good

[ErenYeager97]

I am simulating a LDO (output pole dominant) to regulate a negative voltage from a switching circuit.
The LDO schematic is shown below:

The opamp has open loop gain of 35dB, output capacitor is 2uF with small esr value of 20mOhm. The load resistance
is set to get output current draw around 50mA.

The PSRR starts worse from DC to low frequency and improves at high frequency. The PSRR curves I checked in datasheets,
start high in lower frequencies and get worse at higher frequency.

Here PSRR is shown for two different resistor values:

 

[dick_freebird]

With DC PSRR that low I would suspect that the loop in not closed or the low open loop (the loop entire, not just the error amp) gain is making DC PSRR poor.

However it's also possible that the PSRR expression (which is truncated in the graph legend) may be "something else". Db(Mag(vout)/mag(vin)) plot is here, or if it is not here, looks like what?

 

[D.A.(Tony)Stewart]

Your supply polarity seems inverted to the Op Amp with an NFET.

Why do you have a -Ve Vref input and a +ve Vin going to Vss?