ErenYeager97
Newbie level 6
![Newbie level 6](/styles/images/ranks/blevel3.gif)
I am simulating a LDO (output pole dominant) to regulate a negative voltage from a switching circuit.
The LDO schematic is shown below:
The opamp has open loop gain of 35dB, output capacitor is 2uF with small esr value of 20mOhm. The load resistance
is set to get output current draw around 50mA.
The PSRR starts worse from DC to low frequency and improves at high frequency. The PSRR curves I checked in datasheets,
start high in lower frequencies and get worse at higher frequency.
Here PSRR is shown for two different resistor values:
The LDO schematic is shown below:
The opamp has open loop gain of 35dB, output capacitor is 2uF with small esr value of 20mOhm. The load resistance
is set to get output current draw around 50mA.
The PSRR starts worse from DC to low frequency and improves at high frequency. The PSRR curves I checked in datasheets,
start high in lower frequencies and get worse at higher frequency.
Here PSRR is shown for two different resistor values: