Layout of big transistors

[Junus2012]

Hello friends

Usually in layout design it is highly recommended to devide large transistors to multiple unit size, this help to match different transistors in interdigitized layout and it reduced the gate resistance of wide transistors.

it is suggested by the book of The art of analog circuit to devide the transistors with even number which results in less drain capacitance.

I believe there must be limit for further deviding the transistor or a price that we have to pay, as I learned in analog nothing you gain for free, therefore I would like to ask you about the rule of number of segments, I have read in some publication that he would prefer to devide the transistor untill he has aspect ratio of 10 or less but he didn't explain why

 

[t4_v]

It's like with your current mirror in another topic. Just depends and different persons use different numbers. Just go with 10, then try 20 and see whether everything is ok. In case of layout if you break W = 100 um into 10 x 10 um, everything should be ok. However, if you break W = 100 um into 100 x 1 um, not only you will have a really more work to do (lay out these unit transistors) but your matching may be worse (see Pelgrom Law).

 

[Dominik Przyborowski]

It is process dependent.
Gate leakage with poly resistance makes upper limit for width.
LWR, LER and LOD strain makes lower limit for finger width.
Substrate resistance adds requirements for tap contacts distance and thus might provide constraints for division.
Spatial mismatch might force you to use more sophisticated layout.
High current require more attention for interconnection. Density rules might force higher separation between transistors or limit number of fingers for unit.
Some processes limits area of RX for good matching.
Large area of Poly with specific shape might force uses of more dummies and distance to other blocks (poly is vulnerable for diffraction effects on irregular shape masks).
And more and more...

But don't worry. If you are still using good old C35 nothing mentioned above is an issue.

 

[dick_freebird]

If you're going "big" for high current then the layout will
likely be driven by current flow and reliability. Short and
fat to give maximum interconnect current carrying
capacity and minimum series resistance. Tapered comb
interconnect may drive you to arrange "stripes" of FETs
in non-ortho ways.

Distributing the "reference" device within banks of
slave devices, rather than segregated elsewhere, can
improve matching against thermal and litho gradients.
If the slaves are distributed widely then the impact of
source resistance referred to whatever the "prime
mirror reference node" is, wants some thought (if
the current setpoint amounts to more than a couple
of millivolts).