[SOLVED] Latching issue on storing a value

[dpatel]

Hii -

My first post here. I am trying to store a value on a button press:

num <= switches(7 downto 0) when button = '1';

Now, when I synthesise this it warns of latches on 'num' but that's what I want (to store the value of the switches when the button is pressed). When I try to implement I get an error and can go no further.

I know the latch is because of an incomplete case so if I add an "else" the error goes and everything works.

num <= switches(7 downto 0) when button = '1' else "00000000";

But this means that when I release the button it will set num back to 0!

What am I doing wrong/missing?

 

[FvM]

Causing latch inference isn't exactly an error. So which error message are you actually talking about? Without knowing the involved data types, e.g. of num, we can only guess about possible problems.

 

[dpatel]

OK, sorry for the incomplete info.

num is a std_logic_vector.

The error I get when I 'implement' (mapping stage) is

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <buttons<3>> is placed at site <C4>. The corresponding BUFG
   component <buttons_3_BUFGP/BUFG> is placed at site <BUFGMUX_X3Y6>. There is
   only a select set of IOBs that can use the fast path to the Clocker buffer,
   and they are not being used. You may want to analyze why this problem exists
   and correct it. If this sub optimal condition is acceptable for this design,
   you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
   this message to a WARNING and allow your design to continue. However, the use
   of this override is highly discouraged as it may lead to very poor timing
   results. It is recommended that this error condition be corrected in the
   design. A list of all the COMP.PINs used in this clock placement rule is
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

If I put in the 'else' part as mentioned earlier this problem goes away. So, although not obvious to me, somehow they are linked!

 

[TrickyDicky]

From the looks of it, its trying to make the buttons input a clock, but because its not come in from a clock input, it throws the error above.

Is there any reason you really want latches? any reason you cant use a clock and use the button as the clock enable (and build D types - the much prefered option in FPGAs)

Otherwise you may have to follow the errors advice to covert it to a warning.

 

[dpatel]

Is there any reason you really want latches? any reason you cant use a clock and use the button as the clock enable (and build D types - the much prefered option in FPGAs).

Could you please elborate on this method. I don't want latches but not sure of how to do it otherwise.

 

[TrickyDicky]

process(clk)
begin
  if rising_edge(clk) then
    if button = '1' then
      num <= switches;
    end if;
  end if;
end process;

 

[dpatel]

I see - thanks! I was doing it asynchronously...