npn transistor latch
Assuming you have a picture of the parasitic bjts as a reference which can be found in most cmos text book explaning latchup.
Latch up is basically a positive feedback circuit made up of the paracitic npn and pnp inside your cmos. Remember that to turn on a npn or a pnp, you just need to have that Vbe voltage. There are resistances in your mosfet bulk, drain, source. If the current is big enough and the resistance in the bulk is high enough, it will create that a voltage drop (vbe) and it will start to turn on one of the transistor. This transistor will start to draw current, in which that current will start to turn on the other transistor. Now, since this transistor is turning on, it will in return turn on the original transistor. So, you see a positive feedback going on, and when both transistors are fully on, you have a latch up.
There are a few ways to prevent latch up from happening. One of the easiest way is to dope the bulk layer higher, so that the inert resistivity is low. It will need to have a much higher current to create that initial voltage drop (vbe). If the initial transistor doesn't turn on, then you won't have a latch up.
Of course, doping bulk at a higher lvl means you have a much higher Vt. There is always some tradeoff somewhere.