Is it possible to do a complete latch based digital design for an ASIC ??

[pmat]

Re: Latch based design

Hi,
there is a technique(desynchronization) which converts synchronous
designs to asynchronous ones. All the FFs are removed and latches are
inserted at their position. Take a look at this link:

https://www.ics.forth.gr/carv/async/index.html

pmat

 

[sameer_dlh25]

Re: Latch based design

Hi,

I don't see any issue with the latch timing. I agree that it is diffcult to sign off but is is just a matter of design style.
Latches gives big area and spped advantage over flip flops. Only they impose issue in during the DFT (testability of a chip).
As far as I know Primetime support latch based design since borrowing consept I have seen in it.

 

[archillios]

Latch based design

interesting topic!
as i know, Ti has been using Latch-based or LSSD logic style for their full custom DSP (one old type).
I dont know how they do now.
IBM, another example, they still provide LSSD style design service, but in stage of logic synthesis, designer use only pseudo-cell, common FF, in Physical synthesis and DFT stage, the FFs will be replaced by corresponding LSSD cells.

 

[sumit_techkgp]

Latch based design

Absolutely possible, but development time and timing analysis will be difficult. Further u cannot insert DFT in it. It will be completely untestable.
Sumit

 

[amitk3553]

Re: Latch based design for ASIC

There are some problems in DFT and STA of Latch based design.

Could somebody tell me about these problems?

Thanks




With Regards
cam

 

[maulin sheth]

Re: Latch based design for ASIC

Latch is not totally dependent on clock..so we have not control ability of the latch...so whenever we don't have controllability, DFT insertion problem occur...

 

[ajitrefs]

Re: Latch based design

RAMBO i think make latch based design...

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sry its rambus