Is it possible to do a complete latch based digital design for an ASIC ??

[abhikohli]

Is it possible to do a complete latch based digital design for an ASIC ??

 

[aniketd]

Re: Latch based design

ya it's possible to design a latch based digital circuit
but from implementation point of view in FPGA or ASIC
timing analysis may be critical

 

[abhikohli]

Re: Latch based design

Thanx for the info, Is there any company currently in latch based digital designing ??

 

[aniketd]

Re: Latch based design

there are some companies working in this field
but it's there proprietry design
so it's not possible to mention as i don't know about it

 

[abhikohli]

Re: Latch based design

If latch based design are difficult to analyze by timing analysis tools are there any tools specifically for timing analysis of latch based designs ??

 

[aniketd]

Re: Latch based design

Companies proprietry tools are available for timing analysis
but as they are proprietry they are not availabel to all and i don't think that any one have that information about that tools
but it's critical to analyse asynchrnous circuit

 

[chandhramohan]

Re: Latch based design

Hi ,

Latch based designs give better timing & performance because of its clocking nature ,but the area overhead will be more.

Latch based LSSD design concept is propreitry of IBM & they had their own tools to handle it.Recently few of its tools are taken over by Cadence .The one I know is encounter test architect .

Regards
Chandhramohan

 

[stormwolf]

Latch based design

As i know that LSSD at test encounter is for latch dft. And have nothing about latch design and latch timing analyse.

 

[chandhramohan]

Re: Latch based design

Hi ,
When the dft implemented is latch based ,which I mean all the scan elements are Latch'es , then the design is also Latch based design .For implementing dft logic encounter test architect is used .

I'm not sure which tool is used for Timing analysis for a Latch based design .

Regards
Chandhramohan

 

[aniketd]

Re: Latch based design

can any one know about LSSD i.e Level Sensitive Scan Design??????

 

[sysco_stevens]

Re: Latch based design

complete latch based design is possible,

but it will require multiphase clock.

best regards

Is it possible to do a complete latch based digital design for an ASIC ??

 

[laglead]

Re: Latch based design

It is time and labor consuming to do latch-based ASIC.
There are processors design with latches. But it is full customed.

 

[xuanzhu]

Latch based design

If your design includes asynchronous logic, I suggest that you use latch to do some logic about interface, but I can not believe a full latched chip which does not use Dff triggers

 

[salma ali bakr]

Re: Latch based design

ya it's possible to design a latch based digital circuit
but from implementation point of view in FPGA or ASIC
timing analysis may be critical

Hi ,

Latch based designs give better timing & performance because of its clocking nature ,but the area overhead will be more.

Latch based LSSD design concept is propreitry of IBM & they had their own tools to handle it.Recently few of its tools are taken over by Cadence .The one I know is encounter test architect .

Regards
Chandhramohan

so it has problems in timing analysis and also area overhead...okays
but someone said that it needs multiplephase clock...i'm confused somehow...isn't this latch based design...so it's asynchronous...???

 

[wkong_zhu]

Latch based design

don't use latches as much as possible.

 

[beta0]

Latch based design

Latch based design is usually used for implementation of high performace circuit such as datapath of high performace CPU.

 

[chandhramohan]

Re: Latch based design

Hi ,
The latch based designs are not intended for specific type of logic or design , it can be used in any application .The clocking scheme will be pretty complicated because of multiphase clock input to the latches .

This latch has two latches inside , one acting as master & other one as slave .This latch is controlled by minimum of 3 clocks ( A,B,C ) .This is one of the many type of latches.There are some latches which acts like D-FF .

For simple understanding you can see the doc attached below .

Regards
Chandhramohan

 

[edacw1]

Latch based design

It is possbile. But timing is a very important problom to deal with.

 

[r63511]

Latch based design

ARM Inc. has purchased an IP company so to own an IP which is full latch based design.

 

[modelsim62c]

Re: Latch based design

CPU-designers (Intel, AMD, TI, etc.) have used asynchronous-design strategies to achieve very specific performnace goals, but that's in the territory of PhD and other advanced engineers...not for 'average' persons

For example, the Intel Pentium/4 contained a large portion of 'self-resetting domino' gate-layouts in the speed-critical ALU/datapath. Intel also had an army of engineers to conduct the design/layout/verification of that block of logic, and it's no easy job.

Do a google.com search for 'Pentium self-resetting domino' -- there are a few overviews on the web. To get more detailed papers, you'll need an IEEE or ISSCC subscription.