[SOLVED] irrational clk period

[FvM]

Your question has been already answered, the problem is that you apparently don't understand the answers.

Just run the code in post #1 with any simulation time step resolution according to your requirements, e.g. 10 ps, 1 ps, as you like. The time variable is a real type with sufficient resolution, but the actual wait time interval is rounded according to the simulation time step.

 

[barry]

First of all, your basic premise is wrong. You can't have an "irrational" period. That's a purely mathematical concept.

Set your timing resolution to 1 ps.
Set t_high and t_low=6.849 ns.
Your frequency will be 73003358.1545

 

[ThisIsNotSam]

Yes
Sorry but I do not understand why it is difficult to answer my question

because you are asking it wrong.

 

[mjuneja]

You can try this.

procedure cgen(signal clk : out std_logic;) is
constant P: time := 13698 ps;        
constant HIGH_T : time := P/2;          
constant LOW_T  : time := P/2;  
begin
   loop
   clk <= '1';
   wait for HIGH_T;
   clk <= '0';
   wait for LOW_T;
   end loop;
end procedure;

Just a minor modification in your code.
And ensure time resolution of your simulator to be 1ps.

 

[FvM]

Just a minor modification in your code.

The code in post #1 will achieve the same.

 

[barry]

The code in post #1 will achieve the same.

25 posts and we have now circumnavigated the thread.

 

[JWHassler]

I think post #4 had your answer, or at least outlined the questions you need answered.
You or somebody else must decide on a clock frequency, its resolution and jitter.
Then match these numbers in your simulator.

Also: it's not an 'irrational' period; it's a repeating fraction