Inverter with current mirror

[snang]

Hello everyone, while I was studying inverters, I came across the circuit in the image below, and I couldn’t quite understand it. In this circuit, a current mirror is added on top of the inverter. What is the role of the current mirror in this case?

 

[D.A.(Tony)Stewart]

Do you have any guesses?

 

[dick_freebird]

I have a cell in my current chip design that uses this. I know why.

But handing out answers is not teaching how to think. And this is one that can be thought through. Though you might want application context, likely to hold clues.

If you make three honest (correct or not) guesses I will tell you my reason, what it does. If you're lazy I have better things to do.

 

[snang]

I have a cell in my current chip design that uses this. I know why.

But handing out answers is not teaching how to think. And this is one that can be thought through. Though you might want application context, likely to hold clues.

If you make three honest (correct or not) guesses I will tell you my reason, what it does. If you're lazy I have better things to do.

Thank you for your response. Let me share my thoughts.
First, To control the current (I) and thereby regulate the charging speed of the next stage’s Cgs.
Second, To prevent excessive current flow when the input voltage reaches VDD/2.
Am I right??

--- Updated Wednesday at 4:52 AM ---

Do you have any guesses?

Please take a look at the comment below.

 

[dick_freebird]

In my application, your first guess - with the
downstream C and some "sharpening back up"
you have a current-controlled delay stage
(one-sided - the HL is not strongly affected
except by the drive-strength balance moving
effective inverter DC threshold, the LH can
go from "2 Rds in series" to "open").

I use a "sniffer" bias circuit on a pad, where the
user can hang a set-resistor, to develop user
settable nonoverlap timing in a gate driver.
Force a voltage, take the current, bounce it
back onto the inverter Vdd, badda-bing.