integrating blackbox to VHDL project.

architecture beh of appln is

  signal empty_int,full_int : std_logic;
  signal wr_ptr, rd_ptr     : std_logic_vector(3 downto 0);
  signal wr_en, rd_en       : std_logic;
  signal wr_clk, rd_clk     : std_logic;

  component DPRAM
    port
      (
        wr_clk    : in std_logic;         -- Clock to input port
        rd_clk    : in std_logic;         -- Clock to output port
        wr_en     : in std_logic;         -- Write enable
        rd_en     : in std_logic;         -- Read enable
        wr_ptr    : in std_logic_vector(3 downto 0);  -- write address
        rd_ptr    : in std_logic_vector(3 downto 0);  -- read address
        din       : in std_logic_vector(7 downto 0);  -- write data

        dout      : out std_logic_vector(7 downto 0)  -- read data
        );
  end component;
  
begin

  U_DPRAM: DPRAM
    port map
    (
      wr_clk    => wr_clk,
      rd_clk    => rd_clk,
      wr_en     => wr_en,
      rd_en     => rd_en,
      wr_ptr    => wr_ptr,
      rd_ptr    => rd_ptr,
      din       => din,

      dout      => dout
    );

just declare with the original top-level filename, and install? or do i ahave to do something else too?

=====================================================
*                         Low Level Synthesis                           *
=====================================================
Reading core <wbp.ngc>.
Reading core <pci32tlite.ngc>.
Loading core <wbp> for timing and area information for instance <the_intercon>.
Loading core <pci32tlite> for timing and area information for instance <the_pci>.