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innovus power IO cannot connect with power ring

Starset

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How should I add power IO in innovus?
I use tsmc n28 hpc+ pdk library, and i add the power IO in netlist like this:
1713334599765.png

VDD and VSS is to drive the core, VDDPST and VSSPST is to drive the IO block.
And my IO block is connected as below in netlist file:
1713335588678.png

however, the power IO is still not connected to the power net and there is no pin displayed on the power IO, should I use the createPhysicalpin command? and how should i edit the globalnetconnect command so that i can make the power IO connect to the functional IO and the power net
 
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your verilog looks fine, what you are not showing is your sroute command and sroute settings. there is no need to create pins.
 
your verilog looks fine, what you are not showing is your sroute command and sroute settings. there is no need to create pins.
Here is my globalnetconnection, sroute command and sroute settings, is there any problem? very appreciate your help!

1713354807951.png


1713354837445.png


what I found in apr progress is that the power io pads not only the CORE DRIVER but also the IO DRIVER, they are not connected to the power nets(there is not any wire connected to them), is that correct? thanks!
 
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why are you adding VSSPST and VDDPST rings? they already exist inside the IO cells, they are not needed in the core area.

for the sroute command, you have to call it multiple times. the one example you show seems to be for std cell rails. look into the arguments of the -connect argument.
 
why are you adding VSSPST and VDDPST rings? they already exist inside the IO cells, they are not needed in the core area.

for the sroute command, you have to call it multiple times. the one example you show seems to be for std cell rails. look into the arguments of the -connect argument.
ROGER THAT! i will modify my script! thanks a lot!
 
why are you adding VSSPST and VDDPST rings? they already exist inside the IO cells, they are not needed in the core area.

for the sroute command, you have to call it multiple times. the one example you show seems to be for std cell rails. look into the arguments of the -connect argument.
so your point is that although there is no wire connected with the IO cell(VSSPST AND VDDPST), it still works?
 
there is a wire, it is huge. it runs through the entire pad ring and is fully connected, truly forming a ring around your design. you can inspect the layout of the cells, you will see the pattern. there are rings for VDD VSS VDDPST and VSSPST in some cases.
 
there is a wire, it is huge. it runs through the entire pad ring and is fully connected, truly forming a ring around your design. you can inspect the layout of the cells, you will see the pattern. there are rings for VDD VSS VDDPST and VSSPST in some cases.
Thanks a lot! I appreciate that ! So your point is that there is actually a wire and the io pad is connected but I cannot see that in innovus?
 
Yes, open the GDSII files of the IO cells and you will see the metals I am talking about. Innovus does not represent them because it doesn't have to.
 
Yes, open the GDSII files of the IO cells and you will see the metals I am talking about. Innovus does not represent them because it doesn't have to.
ok i got you! btw i have modified the scripts and solved the problem accroding to your adivse, thanks a lot! what's more, there is another question: if i want to add pad on io cells, should i directly put the pad above the io cell with the command "addInstance"? is there any other issues that i should pay attention to?
 
The bond cell can be placed in different ways. You can do it with relative floorplanning with respect to the IO cell underneath it. You can also use a special command for this, I forget the name but it is something like placeBond or place_bond and it will try to do it for you. In the end, the responsability is still yours to make sure the bond aligns with the IO cell structure. If you get it wrong, you will get DRC violations. If you get it super wrong, you will get a floating bond and no DRC violations. Maybe ERC/LVS violations.
 
The bond cell can be placed in different ways. You can do it with relative floorplanning with respect to the IO cell underneath it. You can also use a special command for this, I forget the name but it is something like placeBond or place_bond and it will try to do it for you. In the end, the responsability is still yours to make sure the bond aligns with the IO cell structure. If you get it wrong, you will get DRC violations. If you get it super wrong, you will get a floating bond and no DRC violations. Maybe ERC/LVS violations.
I got it, I would like to search the command in innovus text command help! btw, very appreciate your help!
 

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