Info about finger layout of CMOS circuit

Hi All


I wonder if you do have any material or introduction about finger
layout of cmos circuit? The below drawing may be a rough drawing, sorry.
For example


--------------------------
| --- --- --- |
| | | | | | | | <------SOURCE
| --- --- --- |
| |
-------------------------------
|<---POLY
-------------------------------
| --- --- --- |
| | | | | | | | <---DRAIN
| --- --- --- |
| |
-------------------------


I do not know how they are connected in circuit , how many mos transistor are there when we draw circuit schematic compare to the layout? I heard that the drain
and source can be interchanged.(What they mean by this?) and the layout will be different compare to circuit. I really cant
figure this out. I hope to understand this fully in circuit schematic
and also layout
Can you give me a good example how to understand this?

Thank you


rgds and thanks
Jason

finger multiplicity cmos

Hi, fingering means to split wide transistors into smalll ones then connect them in parallel. This technique is usually used to get better matching between differential pairs. Hope this helps.
Eric

Re: cmos finger

Drain and Source are interchangable means in layout when we make we do not know which will become drain or source. The terminal having higher potential will become drain for NMOS. Unlike BJT where we have emitter and source to be specific terminals here they are interchangable.

Re: cmos finger

In most PDKs you can see parameter called multiplicity (m) as one of the parameters for MOS device. This one means that total W is divided m times which would be a w for 1 finger.
The reasonse for the finger layout are space and decreasing of parasitic S/D capacitances by sharing the S/D areas.
The layout could look like : S|G|D|G|S|G|D|G|S
In this case your total W = 4xfingerW. You can see and calculate that AD/AS and PD/PS are way smaller and that by reducing this parasitic capacitance you can get faster switching (it is easy to simulate it with string of inverters).

Re: cmos finger

It seems that the 2-finger-gate topology described by Teddy has the smallest drain-bulk parasitic capacitance.

Re: cmos finger

Teddy said:

In most PDKs you can see parameter called multiplicity (m) as one of the parameters for MOS device. This one means that total W is divided m times which would be a w for 1 finger.
The reasonse for the finger layout are space and decreasing of parasitic S/D capacitances by sharing the S/D areas.
The layout could look like : S|G|D|G|S|G|D|G|S
In this case your total W = 4xfingerW. You can see and calculate that AD/AS and PD/PS are way smaller and that by reducing this parasitic capacitance you can get faster switching (it is easy to simulate it with string of inverters).

Click to expand...

Teddy, that's not right. M is multiplier, which means the transistor aspect ration is multiplied by "m". "finger" is another parameter, as you described.

Re: cmos finger

jason

try to get your hands on"The art of Analod layou" by Allen Hastings or any layout book. They will explain very well about fingers, matching when to use and what to use depending on your application

Added after 36 seconds:

correction the book name is Art of analog layout

Re: cmos finger

Thanks a lot to all that responded.
I will try to get that book.
By the way, if anyone has any good link on this topic, kindly share with us


rgds and thanks
Jason