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Hi Sakshi,
Iam not familiar with synopsys formality.
Iam using cadence conformal.I didn't see any issues with caseX and caseZ during formal.Might you can check with synopsys support.
I read somewhere that it's not a good idea to use casex & casez in design .
1. casez treats z & ? as don't care . with casez problem occurs when input goes to high impedence state .
2. In casex there will be issue when input tested by casex will be uninitialized . presimulation will treat it as don't care & post simulation will treat as x resulting in simulation synthesis mismatch
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