In verilog are this parts synthesizable ????

[krishanu007]

Is this parts

1.automatic tasks & functions
2.casez,casex

synthesizable??

 

[chiplogic]

these constructs will be accepted by syntesis tools.
casex,casez will be treated as case statements
automatic tasks & functions will be treated as normal functions and tasks

 

[krishanu007]

so the functionality of automatic tasks & functions,
for which I will be using those,isnt going to be there...
same as casex,casez..
am I right??

 

[YuLongHuang]

casex and casez will be unfolded such that it's syntheisable unless your content is invalid. For example, 3'b00? means 3'b000 ~ 3'b001 which you imply. The function and task can be synthesised if the content is also synthesised. You can treat them as additional submodule which is a small circuit feeding in.

 

[Adam.Yakuvitz]

For quick synthesizability check, we have set up flows with Conformal-LEC. It has one of the fastest parsers in the market and can quickly model a design without needing any library.
> read design rtl.v -golden
> read design rtl.v -revised
> report design data

I set up CAD flows for my company and we have seen customers get design sizes and lots of quick information with this kind of setup. Additionally for those who want to debug their verilog can view schematics and hierarchies of their design with Conformal-LEC.

-- adam

 

[sakshi gupta]

1. System tasks & functions are not synthesisable . Dc gives error while elaborating design .
2. casex & casez are synthesisable in verilog

sakshi

 

[sakshi gupta]

I am just saying that system tasks & functions are ignored by synthesis tools. There is no issue with user defined tasks & functions

regards
Sakshi

 

[krishanu007]

tell me what is the exact behavior of automatic task & functions & casex & casez after synthesis....
are they going to work as they are made for..or they just going to work as a normal task & function & case ...?? :???:
thanx

 

[sakshi gupta]

sorry for the confusion . I think by automatic tasks & functions you mean functions & tasks that are recursive.
1. There is no issues with automatic tasks & functions in synthesis but simulator may hang incase of wrong recursion style .
2. There is no issues with casex & casez after synthesis but formality fails during reference design read if x is used in caseitem in casez

 

[chiplogic]

sorry for the confusion . I think by automatic tasks & functions you mean functions & tasks that are recursive.
2. There is no issues with casex & casez after synthesis but formality fails during reference design read if x is used in caseitem in casez

Formal tools are intelligent enough to treat casex and casez..So formal will not fail...

 

[krishanu007]

so u r telling if everything goes correct then they are will be synthesized & will act according to what they are made for( I mean recursive funda & caring the x,z values in casex,casez)......
:lol::lol:

 

[sakshi gupta]

Yes that's my understanding . what is your thinking ?

 

[krishanu007]

Formal tools are intelligent enough to treat casex and casez..So formal will not fail...

I am a newbie ....so...what do u mean??

 

[sakshi gupta]

I used x in caseitem in casez statement . Formality was failling . You can try this on small testcase

 

[krishanu007]

Yes that's my understanding . what is your thinking ?

Its really awkward to think that in circuit...how a combinational function block will be called totally seperately,because its physically a single block.(& dont tell there will be a synchronizer block with temporary registers to handle this)
& how a x values & z values will get detected in a circuit....are there any readymade circuit block available for implementing this function-( leaving how).

Up to I know its awkward( again) that a synthesizer will add additional circuits for making a synchronized function block( like a scheduler for a processor for handling multiple threads)...
See how greatly confused I am...:shock::shock:

---------- Post added at 09:56 ---------- Previous post was at 09:54 ----------

I used x in caseitem in casez statement . Formality was failling . You can try this on small testcase

That is obvious ...but come to the point of hardware blocks working what is intended for.....

 

[chiplogic]

Hi krishanu007,
recursive functions mainly for simulation purpose..
I dont think it is a good idea to use recursive functions in real hardware
synthesis tool tries to unfold the recursive function if possible depends on your exit condition..it will add series of redundant combinational block to implement the functionally..say like serial addition.
To be frank i never come across recursive functions in proper designs meant for hardware implementation.

Hi Sakshi,
Check your modelling options in your formal script to treat X/Z as don't cares.

 

[krishanu007]

Hi krishanu007,
recursive functions mainly for simulation purpose..
I dont think it is a good idea to use recursive functions in real hardware
synthesis tool tries to unfold the recursive function if possible depends on your exit condition..it will add series of redundant combinational block to implement the functionally..say like serial addition.
To be frank i never come across recursive functions in proper designs meant for hardware implementation.

Hi Sakshi,
Check your modelling options in your formal script to treat X/Z as don't cares.

yes..
good thinking...but It still remained in the darkness of "its not a good idea to do"....
May be I need to ask some manufacturer for this...

 

[sakshi gupta]

I also agree not to use recusrsive functions in design .

What do you mena you modelling options in Formality ?

 

[krishanu007]

I also agree not to use recusrsive functions in design .

What do you mena you modelling options in Formality ?

I dont mean modeling..I mean designing real circuits..
are there any tool which will directly tell me about code that its synthesizable or not.....???

 

[chiplogic]

I also agree not to use recusrsive functions in design .

What do you mena you modelling options in Formality ?

HI Sakshi,
Which tool you are using for formality.
How you formal tool is treating non-constant(X or Z) values in your design ?