Improving signal shape of single-ended ECL D-FF Output?

termination of single-ended ecl

I'm using ON Semi's ECLinPS Lite and Plus ECL D-Flip-Flops like MC100EL31 and MC100EP31. My circuit has single-ended connections and there is no way to use differential connection.

The problem is that these two D-flip-flops "leak" clock signal to the outputs (Q, /Q). The clock crosstalk to the outputs is very large (20-30 %)! Since I'm using single-ended connections, Q (or /Q) has very bad "logic" shape so I'm having problem with distorted logic signals.

What are my options to reduce clock signal from Q and /Q outputs of the D flip flop?

Any help would be greatly appreciated!

cheerio,
rfmw

edit:

I have NECL configuration, so Vcc pin is connected to the microstrip groundplane with practically no inductance (well I cant eliminate internal package inductance, right? . Vee pin is decoupled to groundplane with 0603 100nF with minimal trace lengths and practically no via inductance... The problem is internal clock crosstalk to the outputs

How to improve signal quality of single-ended D-FF Output?

What clock rate are you using? Try slowing down the clock to see if the ugly signals change shape or improve.

Single-ended ECL signals should look pretty good, if you have provided correct layout and termination. However, if you are trying to measure hundreds of MHz signals using ordinary scope probes with ground leads, then you need a better probing method.

Re: How to improve signal quality of single-ended D-FF Outpu

Thanks for replying

What clock rate are you using? Try slowing down the clock to see if the ugly signals change shape or improve.

Well, I'm pushing these ECLinPS Lite and Plus chips to their upper limit My clock frequency is 2.5 GHz (2.5 Gbps circuit with NRZ pseudo-random data ... bandwidth from few MHz to clock freq) and the datasheet states that its maximal toggle rate is at approx 3 GHz... Sure, if you lower the clock frequency of the D flip flop, clock crosstalk to the outputs lowers as well, but I simply cant lower my clock frequency....

Single-ended ECL signals should look pretty good, if you have provided correct layout and termination. However, if you are trying to measure hundreds of MHz signals using ordinary scope probes with ground leads, then you need a better probing method.

I've taken great care designing the PCB. Passive S21 and S11 measurements of the PCB showed good results. My ECL termination is parallel (50 ohms to Vtt-well decoupled to the microstrip groundplane). I think the only problem are ECL D flip flops, so again my question, how to eliminate clock signals from their outputs?

Direct DC-termination to 20GHz BW 50 ohm oscilloscope and high-impedance probe measurements showed approx the same results...2.5Gbps data which includes high clock amplitude, grrrr

thanks again mate

I've had experience where at 2.5 GHz clock inputs, dielectric loss due to the PCB board was causing a loss of about -1 dB/inch of trace. The results was that end input signal to the clock input had attenuated to a point where the clock inputs could not switch fully, therefore causing a mixing of signals between the track and strobe conditions of the latch. In another words, increase the input signal to the clock input if possible.

Else, you can buffer the data and clock inputs with a driver, such as the EP16, to minimize the clock feed thru. Drawback is that you need to buy more parts ($$$), redesign your PCB, and your system power will increase.

krashkealoha said:

I've had experience where at 2.5 GHz clock inputs, dielectric loss due to the PCB board was causing a loss of about -1 dB/inch of trace. The results was that end input signal to the clock input had attenuated to a point where the clock inputs could not switch fully, therefore causing a mixing of signals between the track and strobe conditions of the latch. In another words, increase the input signal to the clock input if possible.

Click to expand...

Yes, I noticed relatively high attenuation also (approx 1.5 dB attenuation on 2.5 inch FR-4 tinned trace). But this can be simply resolved. Instead of feeding the ECL with 2 dBm (800mVpp) sinewave to drive 50 ohm trace to flip flop clock input, one can just increase the level to 3-5 dBm and problem solved. However this not the problem I'm experiencing...

Else, you can buffer the data and clock inputs with a driver, such as the EP16, to minimize the clock feed thru.

I'm not sure what you mean here exactly. Could you be more specific?

Thanks,
rfmw

Sorry for the late response.

What I meant was to have a one EP16 drive the data inputs of the latch, and another EP16 drive the CLK inputs. Hopefully, the EP16 devices provide some type of buffering or isolation between the latch and the source signal. (I haven't checked to see if the VIH/VIL levels for the data inputs and clock inputs are the same such that you can do something like this).