improving power supply stabilizer circuit question

[yefj]

Hello,I Have simulated the circuit with a certain source but still I have a section where there is a slope on -12V as if we need the pulse to happen later.
How do you recommend to get rid of the slope shown below in the photo.
LTspice files is attached.

 

[D.A.(Tony)Stewart]

Look at your LED current. You do not have a DC OK signal.

 

[yefj]

Hello Tony,I managed to solved this issue by playing with R4 to 1k.
what do you mean "DC OK signal" what component? what Pin signal I missed?

 

[D.A.(Tony)Stewart]

Which intermediate node detects the state of each input voltage is within tolerances?
And what is that threshold and tolerance? >90% of 12V (?)
Where are your design specs?

 

[yefj]

Hello, the goal is 12V -12V ,0.5V distance threshold.so 11.5 is ok.
What component what pin you saw has problematic signal?
Thanks.

 

[D.A.(Tony)Stewart]

I(R9) My point is there is no signal to say DC is OK and your control signals start before +/-12V supplies are OK. Is that what you want?

 

[yefj]

Hello Tony,As you can see below when my R4 is 1K the outputs are almost perfect.
The R9 i got is shown below.
A red flag to me is some result that contradicts a data sheet.
It differs your R9 current plot.
Could you see something which is problematic that will blow up my circuit or will not produce the perfect +12 -12 result i get in the simulation output?(datasheet wise)
Thanks.

 

[D.A.(Tony)Stewart]

You seem to come up with asynchronous analog questions without clear goals.

We have suggested a synchronous state machine, yet you do not seem to appreciate the significance of controlled design specs and expected results. Rather you are following an amateur approach of trial and erorr with unstated assumptions.

FWIW Your symbolic model should be a dual FET P-N pair and show pins for DSG.
Your switches are asymmetrical and asynchronous. Why?
+12 uses common emitter Opto to Pch FET with input risetimes gated to the output near 10V. i.e. not a good result.
-12 uses common collector Opto to Nch FET ... ditto near -2V not a good result. The differences are visible when your risetimes are in "us"


You waste space in the schematic and should use "net" tags to plot to make it easier to recognize.

I still would expect you to define the performance 1st. i.e. system design specs.
then realize specs with a design that covers all requirements
then verify performance (DVT)
then ask for help when it almost works but has an unexpected problem.
We can review but we want you to do the work and follow advice.

Otherwise, your progress will be slow, and your design methods will go in circles and keep missing the undefined measurable specs.

 

[yefj]

Hello Tony,I dont understand the meaning of this sentence.
The output pin 10 drain pin 10 is 12V not 10V.
Where do you see 10V?

.SUBCKT DMG6602SVTQ_N 10 20 30
* TERMINALS: D G S

"Pch FET with input risetimes gated to the output near 10V. i.e. not a good result."

 

[D.A.(Tony)Stewart]

Look at all your signal currents and see the low S/N margin

 

[BradtheRad]

I'm reading this latest discussion with the altered schematic. I confess I'm running out of new approaches. ThinkIng through the steps in my mind I uncover details which are hard to sort out and weigh -- let along solve.

There's the quandary that we want to make devices decide (electronically) whether or not to convey a supply rail (positive, negative, or both) while those devices are running on the very same supply voltages on which the question revolves.

And wasn't this startup sequence intended to fit into a longer startup sequence of events which energize a cascade of events?...
If we (Yefj) could hit on a building block that's expandable to do these things... and also allow shutdown in reverse order.