Improving Jitter in PLL circuits

[chris jones]

Hi guys, I wondered if anyone knew the answer to this general question?

Lets say I have a phase locked loop circuit. It has an EXOR gate that accepts a 1.024MHz feedback frequency. The EXOR goes to a low pass filter and the Low pass filter drives a Voltage controlled oscillator. The output of the VCO is 32.768MHz. The 32.768MHz is divided down by a set of D-type bistables and fed back into the EXOR. this is the 1.024MHz mentioned earlier.

All that above works just fine.

I am putting another 1.024MHz signal into the EXOR and this reduces the jitter a bit.

My question is:

would I get less jitter if I used a higher feedback frequency?

 

[dick_freebird]

The input edge rates to the phase detector matter more
than the simple frequency. Though higher frequency can let
you filter things better. You might also want to be looking
at the supply / ground quality in your divider chain and the
phase detector.

Have you looked at the reference frequency for its intrinsic
jitter (say, by locking on a rising edge and B-delayed
'scope mode looking at another edge many cycles later)?

Absolute jitter measurements on the bench can be tough;
you can learn a lot from looking at things on a "contributed
jitter" basis if you have a reasonably low incoming jitter
though.

 

[chris jones]

Thanks for your reply. I could look at the supply rails.

 

[biff44]

Depends on what you mean by "jitter". If you are worried about pS of jitter, then yes...a higher reference frequency will help--but not for the reasons you probably thought of. You have a 32 Mhz oscillator. You are dividing down by 32. That means that you are getting an output from the divider chain every ~ 1 uS in time. So every 1 uS, your EXOR gate is putting some sort of pulse into the lowpass filter. It might take many pulses, perhaps 50 of them, to appreciably change the voltage on the capacitor of the lowpass filter.

So, lets say something perturbs your VCO. It will take 50 x 1 uS = 50 uS before your loop has settled out and fully corrected for the perturbation. That allows a lot of "chatter" in the actual VCO output. If you have a periodic noise perturbation (like a switching voltage regulator), your VCO/PLL might be chasing its tail all the time and never settling out.

So by increasing the reference frequency, you are lowering the divisor ratio, and thereby decreasing control loop dead time (transport lag if you want to be technical), and everything will work a little better.

But you have really not explained what you are doing. Is the VCO very stable (like a crystal or saw oscillator), or is it jumping around all over the place. Is the reference frequency input more or less stable than the VCO. You have to carefully choose your PLL bandwidth on the basis of how you answer that question.

Rich

 

[chris jones]

Hi,
Just to let you know the VCO is not jumping around all over the place. It is pretty stable as is, were just looking at way to make it slightly better.

I had a gut feeling that increasing the frequency would reduce jitter. Im not expecting miracles just small improvements, and really it was a hypothetical question.

In my system the main 32.768MHz timebase is generated by a Citizen CSX -750V VCO, A voltage controlled Crystal Oscillator. This is pretty stable.

We are trying to improve the stability by injecting the output of an OCXO into the PLL chain. My tests show that the divided down frequencies remain stable for much longer periods of time when we do this.

 

[biff44]

Well, I hope you realize that the 32 MHz signal, after is is divided by 32, will "look" like it has lower jitter, but it is exactly the same jitter just divided by 32! Conversely, your master clock at 1 MHz will have to be much better than 32 times as good as the 32 MHz oscillator for you to be able to lock the two together and get any improvement.

Another way of saying this is if your 32 MHz oscillator has a phase noise of -120 dBc/Hz at 1 KHz offset, to improve this by locking to a 1 MHz oscillator, that 1 MHz oscillator had better have phase noise MUCH better than -150 dBc/Hz at 1 KHz offet. This is because the pll will act as a frequency multiplier X32, which is a 30.1 dB degradation of phase noise (20 * LOG 32 = 30.1 dB).

So, IF your 1 MHz oscillator is indeed much more than 30 dB better in phase noise than your 32 MHz oscillator, you can try to improve things by phase locking the two together. Then you have to play around with the PLL control loop bandwidths to get things just right.

You sould try to add a big capacitor, like a 47 uF tantalum, right at the 32 MHz VCXO's Vdd pin, and see what happens.

A common use of the PLL and its bandwidth is to improve the noise of a VCO close to the carrier (perhaps within +/- 20 KHz of the carrier frequency) by locking the higher frequency VCO to a very stable low frequency XTAL oscillator. But at higher offset frequencies, where the VCO's free running phase noise will be better than the XTAL's phase noise when degraded by the 20LogN multiplication effect, you close out the PLL control bandwidth and let the VCO run free. So, at typically 200 KHz, your PLL is having no effect on the VCO any more.

 

[chris jones]

47uF at the supply to the VCXO? Hmm sounds like an idea. I might try that at some point and see what happens.

 

[karesz]

... your master clock at 1 MHz will have to be much better than 32 times as good as the 32 MHz oscillator for you to be able to lock the two together and get any improvement.....

Hi,
Especially if you will select a so called "High Q" 1MHz resonator!:_)
Formerly they are in relative bulky glass tubes as valves & has at 100(or more) time higher Q/cleaner resonance_smaller phase noises as generell types...
K.

 

[biff44]

I am assuming something like a silicon bipolar low phase noise crystal oscillator at 1 MHz.

As far as the 47 uF, I know it is big, but in some cases your phase noise will improve significantly. Expecially if you are talking about low data rate systems or radars where the close-in phase noise is critical. The problem is that most voltage regulators only clean up DC noise in the 20 KHz or so region. By the time you get to 1 MHz, they are all pretty much out of ripple rejection capacity. You need passive R-C filtering as well as a good low noise voltage regulator.