[SOLVED] if statement within a generate for loop

[jasmine123]

The algorithm:

Z=0;
for (i=0;i<n;i++){
{Z=Z+j[i]k;}
if (Z%2=1)
{ Z=Z+M;
   Z=Z/2;
}
else 
{Z=Z/2;}}
if (Z>M) {Z=Z-M;}

The code i have written is as:

module monto_arithmetic(j,k,n,y);
      input [7:0] j,k,n;
      output reg [7:0] y ;
      wire [7:0] p [0:7];
      wire [7:0] r [0:8];
      wire [7:0] l [0:8];
      wire o [0:7];
      wire g [0:7];
      wire [7:0] f;
      assign r[0]=8'b0;
      genvar i;
      generate for (i=0;i<8;i=i+1) begin:block1
          conditional_bit c0 (j[i],k,p[i]);
	  adder_8bit_reversible t0 (p[i],r[i],1'b0,r[i+1],o[i]);
	  assign f=r[i+1];
	   if (f%2==1'b1) begin:block2
	   adder_8bit_reversible t1 (r[i+1],n,1'b0,l[i],g[i]);
	   assign l[i]=l[i]>>1;
	   assign r[i]=l[i];
	   end
           else begin
	   assign l[i]=l[i]>>1;
	   assign r[i]=l[i];
           end
     end
     endgenerate 
     assign y[7:0]=r[8];
     always @*
     begin
     if (y>n)
     assign y=y-n;
     end
     endmodule

ERROR:HDLCompilers:277 - "monto_arithmetic.v" line 36 Illegal condition expression in generate
if statement

Can somebody point the mistake?

 

[vGoodtimes]

f isn't a genvar. I think you want to instantiate the modules and then conditionally use the results.

 

[jasmine123]

The result of t0 which is r[i+1], I need to check if it is even or odd and the do the respective computations. Since f is 8bit, I cannot declare it as genvar . It again causes error.

 

[pbernardi]

I do not think you can use a "conditional generate" as you want (not completely sure however).

The easier way I think is rethink the concept: make the generate to count to half (4 instead 8 in your example) and then generate two blocks: one for odd and other for even.

 

[ads-ee]

The f%2 is a problem in the if. If you want to check for even/odd values f[0] is what you perform the compare with, and then I wouldn't even use a compare...

if (f[0]) begin : block1 // if f odd

Haven't looked carefully at the rest of your code, but one observation is that you look like you don't care if the circuit is fast as you've got multiple passes through a bunch of combinational blocks instantiated multiple times. Direct translation of software loops usually end up this way. As the previous poster stated you should "rethink the concept".

FYI HDL stands for Hardware Description Language. If you want to write C code and turn it into a circuit you should invest in Catapult C or one of the other HLS tools, instead of directly translating C code (or pseudo code) into Verilog)

 

[vGoodtimes]

Looking at this again, I think the entire thing has flaws.

The syntax error is because f[0] is a wire, but is used to generate an instance of the adder. f[0] isn't constant at compile time so the tools don't know what you want.

But the rest of the code has multiple assignments to the same nets (within the same cycle) as well. These aren't syntax errors, but the design won't simulate correctly or synthesize.

 

[FvM]

Do you understand that any condition evaluated in the generate construct must only depend on genvars and constants known at compile time? It doesn't look like array r complies to this prerequisite. If it's constant though, you may need to change the evaluation method.

 

[slutarius]

Look at this example and I am thinking about software trap to hardware designer.
Still, it happends.

If you break down the C code and take note on where intermediate variables have been used,
it can be considered as FlipFlops on hardware code.
A C for loop can be turned into a FIFO on hardware code.

The rest of things are wires and functions.