ICC - SNPS_LOGIC nets

[manchuk]

IC Compiler inserts some SNPS_LOGIC0 and LOGIC1 nets. I am not sure why they are inserted. What is its significance. How can I eliminate or rename them ?

 

[randyest]

These are nets that, based on your logic (RTL) will always be 1 or 0. So synthesis disconnects those nets from whatever logic was driving the nets and attaches them to "Logic_0" or "Logic_1" since there is no need for the logic state to ever change. The tool thinks these should be connected to VDD or GND in the backend.

Some ASIC vendors or fabs don't mind if you leave it as "Logic_0" or "Logic1" or connect direct to VDD/GND, but some want you to change "Logic_0" or "Logic_1" to connect to the pin of a special clamp cell that ties the signal level to '0' or '1' level.

 

[manchuk]

@randyest..thanks for the reply. There is a command to remove the tieoff cells. Would you be knowing the implications of using that ?

 

[randyest]

@randyest..thanks for the reply. There is a command to remove the tieoff cells. Would you be knowing the implications of using that ?

Well, if you remove tieoff cells (clamp cells) DC will connect those constant 0/1 nets to VDD, or VSS, or generic "Logic_0" or "Logic_1" nets. This may or may not be what you want, depending on your ASIC vendor / fab.

If I were you I'd ask my ASIC vendor/fab what they prefer for tied high/low nets. You might also be able to tell from checking your block library or design manual documents. Sorry I can't be more specific, because not all fabs/vendors want the same thing. But if you want to post (or PM me) your vendor/fab I might be able to share more details.