These are nets that, based on your logic (RTL) will always be 1 or 0. So synthesis disconnects those nets from whatever logic was driving the nets and attaches them to "Logic_0" or "Logic_1" since there is no need for the logic state to ever change. The tool thinks these should be connected to VDD or GND in the backend.
Some ASIC vendors or fabs don't mind if you leave it as "Logic_0" or "Logic1" or connect direct to VDD/GND, but some want you to change "Logic_0" or "Logic_1" to connect to the pin of a special clamp cell that ties the signal level to '0' or '1' level.