I want to multiply a OCXO square wave output,anyone could give me some suggestion?

[fenfei]

　I have a 10MHz OCXO,now I need to multiply it to 50MHz,and keep the residual phase noise of multiplier circuits as low as possible. anyone could give me some suggestion?

the PLL is not good,the noise floor of PFD is too high .

 

[biff44]

just use a 50 MHz bandpass filter, and amplifiy the output.

 

[vfone]

Two-Diode Odd-Order Frequency Multipliers

 

[fenfei]

just use a 50 MHz bandpass filter, and amplifiy the output.

The OCXO output is TTL square wave output,how do I design the bandpass filter?
I mean the input and output impedance.

 

[biff44]

I am not sure what the output "impedance" of a digital gate is. But whenever I have done this in the past I just chose a bandpass filter topology that had a series capacitor as the input element (to not load down the gate too much). I designed the filter for 50 ohms in/out, and adjusted the values during test to get the bandpass centered on the 5th harmonic, and the series input cap coupling to be optimized for best power without letting in the other harmonics too much.

The power level will be pretty low (maybe -10 dBm) so you will have to reamplify it to use anywhere useful, so you know the load impedance to the filter (that amplifier's input impedance).

 

[fenfei]

I am not sure what the output "impedance" of a digital gate is. But whenever I have done this in the past I just chose a bandpass filter topology that had a series capacitor as the input element (to not load down the gate too much). I designed the filter for 50 ohms in/out, and adjusted the values during test to get the bandpass centered on the 5th harmonic, and the series input cap coupling to be optimized for best power without letting in the other harmonics too much.

The power level will be pretty low (maybe -10 dBm) so you will have to reamplify it to use anywhere useful, so you know the load impedance to the filter (that amplifier's input impedance).

Thanks!
My OCXO phase noise is as low as -155dBc/Hz@10kHz.should I use an OP or a low noise amplifier after the filter,which has a lower residual phase noise?

---------- Post added at 16:23 ---------- Previous post was at 16:21 ----------

Two-Diode Odd-Order Frequency Multipliers

But my OCXO is TTL output, not 50 ohm sine wave.

 

[biff44]

Thanks!
My OCXO phase noise is as low as -155dBc/Hz@10kHz.should I use an OP or a low noise amplifier after the filter,which has a lower residual phase noise?

---------- Post added at 16:23 ---------- Previous post was at 16:21 ----------


But my OCXO is TTL output, not 50 ohm sine wave.

You realize that low noise figure does not necessarily equate to low phase noise!

If you go thru the math, if the 5th harmonic is -10 dBm, and the bandpass has 3 dB loss, you are getting pretty close to thermal noise floor limits with a -155 dBc phase noise signal. You will want a 2 dB noise figure or better in the amplifier.

 

[tony_lth]

You can 1st use a buffer amplifier to amplify the OCXO output, put the amplifier in satruated state, then 5th bandpass filter, and amplify again.

 

[biff44]

That is a good idea, although it is a little complicated by the fact that you have a saturated amp driven by a multitone signal. Due to 3rd order and 5th order products, if you are unlucky you might end up with the 5th harmonic being eradicated instead of amplified. But it is worth the risk if you are willing to make sure the intermods are not screwing things up.

 

[G0HZU]

If you multiply the 10MHz to 50MHz you will get a phase noise degradation of about 14dB so your -155dBc/Hz at 10kHz will degrade to -141dBc/Hz (or worse) at 10kHz when you remeasure the phase noise at 50MHz.

What is the frequency plan of your PLL? Are you sure multiplying the 10MHz will help reduce the PLL noise?

Are you planning to run the phase detector at 50MHz rather than 10MHz?

 

[biff44]

Thanks, that is a very good point. Even though you are only using the 5th harmonic, its phase noise will degrade just like if you multiplied it by X5. Therefore, the nf of the amp is a lot less important!

 

[fenfei]

Thank you!
IN theory,higher PFD freq,lower phase noise in PLL.I know the multiplier N means 20logN degradation in phase noise.I have decide to use a low noise amplifier to amplifier the filter output.

 

[tony_lth]

Are you sure multiplying the 10MHz will help reduce the PLL noise?

Are you planning to run the phase detector at 50MHz rather than 10MHz?

If He adopt 50M PDF, he will get 7dB improvement in phase noise than 10M.

 

[biff44]

Wow, this thread took a roundabout turn! Let me summarize:

You have a 10 MHz OCXO with -155 dBc/Hz phase noise at 10 KHz.
You want to use that as a clock for a PLL. The PLL can use a clock at either 10 or 50 MHz, and you want the best overall phase noise of the locked oscillator.

So, no matter how you get to a 50 MHz clock, the phase noise of the 50 MHz clock will be 20 Log (5) worse, or -141 dBc/Hz.

The thing you do not tell us is the type of PLL chip. If that chip has a phase noise floor of maybe -160 dBc/Hz, then you can run it with a 10 or 50 MHz clock and there will be pretty much no difference. I would choose the 10 Mhz clock because the hardware is easier.

If, instead, the PLL chip had a worse phase noise floor (say -150 dBc/Hz), then using a 10 MHz clock with -155 dBc/Hz noise is going to degrade that clock, and you would be worse off. If you used the 50 MHz clock, its -141 dBc/Hz noise is much better than the PLL's -150 dBc/Hz, so in that case you should multiply x5, or use the 5th harmonic, to get the clock to 50 mhz.

 

[tony_lth]

Such as ADF4113 etc., its noise floor is about -206dbc/Hz. The VCO output in band phase noise is: Phase Noise=(1 Hz Normalized Phase Noise Floor from Table) + 10* log(Comparison Freq) + 20*Log(N)
e.g. 900MHz VCO; Fcomp=200KHz; N=4500; Use LMX2315; Phase Noise=-206+10*Log(200,000)+20*Log(4500)=-80dBc/Hz
So if use 50M clock, the comparison freq X5, but N is /5. So maybe get 7dB improvement in phase noise.

 

[fenfei]

Wow, this thread took a roundabout turn! Let me summarize:

You have a 10 MHz OCXO with -155 dBc/Hz phase noise at 10 KHz.
You want to use that as a clock for a PLL. The PLL can use a clock at either 10 or 50 MHz, and you want the best overall phase noise of the locked oscillator.

So, no matter how you get to a 50 MHz clock, the phase noise of the 50 MHz clock will be 20 Log (5) worse, or -141 dBc/Hz.

The thing you do not tell us is the type of PLL chip. If that chip has a phase noise floor of maybe -160 dBc/Hz, then you can run it with a 10 or 50 MHz clock and there will be pretty much no difference. I would choose the 10 Mhz clock because the hardware is easier.

If, instead, the PLL chip had a worse phase noise floor (say -150 dBc/Hz), then using a 10 MHz clock with -155 dBc/Hz noise is going to degrade that clock, and you would be worse off. If you used the 50 MHz clock, its -141 dBc/Hz noise is much better than the PLL's -150 dBc/Hz, so in that case you should multiply x5, or use the 5th harmonic, to get the clock to 50 mhz.

You are right, there is another reason that PLL chip datasheet says in 10MHz the PFD noise floor will worse 5dB than in 50MHz

 

[biff44]

Such as ADF4113 etc., its noise floor is about -206dbc/Hz. The VCO output in band phase noise is: Phase Noise=(1 Hz Normalized Phase Noise Floor from Table) + 10* log(Comparison Freq) + 20*Log(N)
e.g. 900MHz VCO; Fcomp=200KHz; N=4500; Use LMX2315; Phase Noise=-206+10*Log(200,000)+20*Log(4500)=-80dBc/Hz
So if use 50M clock, the comparison freq X5, but N is /5. So maybe get 7dB improvement in phase noise.

The phase noise floor of the ad pll is NOT -206, I assure you it is in the -145 to -160 range. They just curve fit some data to include the actual reference frequency.

 

[ledum]

If we choose low noise VCXO, something like Driscoll's Crystal Oscillator Topology http://uwsdr.berlios.de/A New LNXO Topology.pdf , for example, and PLL chip like ADF4002 with lowest noise floor and choose very narrow PLL loop bandwidth (100-200Hz at 10MHz PHD), we will obtain phase noise at 10kHz from carrier 50MHz , which is defined only by phase noise of VCXO and frequency instability, which is defined by OCXO. Look Attachment, pls
We use this topology with AD9510 to x9 10MHz OCXO and to fanout it into 4 different low jitter clocks 90MHz

 

[Dr.Drew]

Using article about waveform conversion at Wenzel site you can calculate a matching circuit for 5ft harmonic filter. Be careful with filter design. Subharmonics can cause a 10 MHz spurious in PLL output spectrum. After harmonic filtering you can amplify a signal using IF MMIC such as SGA-2363 or similar.
Another way is to amplify a 10 MHz signal and multiply it to 50 MHz with diode frequency multiplier or UHF varactor diode (BBY52-02 for example) harmonic generator. First one may be used for multiplication factors up to 5, second one - for factors up to 10-20. This way is more attractive for ULN sinewave output OCXO with phase noise 174-170 at 100 kHz offset.
Third way posted by ledum (Hi!). But be careful with subharmonics.

 

[ledum]

IF MMIC such as SGA-2363 or similar

Hi! I prefer something of pure silicon, like MSA-0386, or InGaP, like GALI-59, not heterostructures, like SiGe.