i got error in the generate statement help me to rectify it

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Shyam Joe

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this is my coding
Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [256:0] v1,w1,v2,w2;
parallelreg a1(
	.din	(256'b0),
	.clk	(clk),
	.rst	(1'b1),
	.dout	(s1)
);
parallelreg a2(
	.din	(256'b0),
	.clk	(clk),
	.rst	(1'b1),
	.dout	(s2)
);
flp a4(
	.u		(u),
	.v		(v1)
);
notb a5(
	.a		(s2),
	.y		(s3)
);
muxb a6(
	.a		(s1),
	.b		(s3),
	.s		(co),
	.y		(s4)
);
bitadd a7(
	.a		(s1),
	.b		(s4),
	.cin	(co),
	.c		(v2)
);
notg a8(
	.a		(co),
	.b		(c3)
);
notb a9(
	.a		(p),
	.y		(a5)
);
muxb a10(
	.a		(p),
	.b		(s5),
	.s		(c3),
	.y		(s6)
);
bitadd a12(
	.a		(v1),
	.b		(s6),
	.cin	(1'b1),
	.c		(w1)
);
bitadd a13(
	.a		(v2),
	.b		(s6),
	.cin	(c3),
	.c		(w2)
);
org a14(
	.a		(w1[256]),
	.b		(v1[256]),
	.y		(c1)
);
org a15(
	.a		(w2[256]),
	.b		(v2[256]),
	.y		(c4)
);
muxg a16(
	.a		(v2[256]),
	.b		(c4),
	.s		(c3),
	.y		(c2)
);
muxb a17(
	.a		(w1[255:0]),
	.b		(v1[255:0]),
	.s		(c1),
	.y		(t1)
);
muxb a18(
	.a		(w2[255:0]),
	.b		(v2[255:0]),
	.s		(c2),
	.y		(t2)
);
parallelreg a21(
	.din	(a),
	.clk	(clk),
	.rst	(1'b0),
	.dout	(s1)
);
parallelreg a22(
	.din	(b),
	.clk	(clk),
	.rst	(1'b0),
	.dout	(s2)
);
generate
genvar i;
for(i=255;i>=0;i=i-1)
begin: ABC
muxb a3(
	.a		(s1),
	.b		(s2),
	.s		(b[i]),
	.y		(u)
);
muxb a19(
	.a		(t1),
	.b		(t2),
	.s		(b[i]),
	.y		(a)
);
muxb a20(
	.a		(t2),
	.b		(t1),
	.s		(b[i]),
	.y		(b)
);
end
endgenerate
endmodule
i got this error..
=========================================================================
WARNING:HDLCompilers:261 - "fpunit.v" line 23 Connection to output port 'v' does not match port size
ERROR:HDLCompilers:246 - "fpunit.v" line 47 Reference to module 'notb' is not a legal net lvalue
ERROR:HDLCompilers:102 - "fpunit.v" line 47 Connection to output port 'y' must be a net lvalue
WARNING:HDLCompilers:259 - "fpunit.v" line 56 Connection to input port 'a' does not match port size
WARNING:HDLCompilers:259 - "fpunit.v" line 62 Connection to input port 'a' does not match port size
plz help to rectify it
 


first error is because you have 255:0 u and 256:0 vl so port size not mached (probebly)...
the second is because you connect to your output to componenet instance a5 instead of wire.
thirs error again v1 , s6 not same size 255:0 u and 256:0....
 

Shyam Joe,

First a question. Why are you developing your code using a bunch of very simple instantiated modules? Doing this makes code virtually unreadable and unmaintainable. If this is for a school project and the instructor told you to do it this way...I retract my question (though IMHO it's stupid to teach Verilog design this way, no company I've worked for would tolerate an employee writing code like this).

Some comments/observations:
c1. use better names, single character and signal character+number are very difficult to read and maintain. (proven by your mistake on line 47 where you have .y (a5) a5 is the name of your notb a5( instance. If you had used notb notb_1( for the instance name you wouldn't as easily have this problem. Come up with meaningful names for your interconnecting wires.

c2. If you have to write code like this (many tiny modules) use comments and white space to make things more readable.

o1. what is up with notb and notg, why have two different modules with what I assume are NOT gates inside? Do they have different port widths? If so why didn't you use a parameter to define the port widths?

o2. why use for(i=255;i>=0;i=i-1)? This is the first time I've ever seen someone use the for loop with a decremented inedex. for(i=0;i<256;i++) If all your tools support System Verilog or for(i=0;i<256;i=i+1). Personally I prefer this as I typically start at a count of 0 and the number of counts through the loop is the same as the compare.

o3. Is .rst (1'b1) and active low reset? I would add something like _b or _n to the end of the name rst to make it easier at a glance to know it's active low. If it wasn't active low they you've got a problem having your register always in reset.

You should really look around and find a coding style guide for Verilog or a SW coding style guide (which you can adapt to Verilog).

Regards
 

When i modify the code as like this
Code: 
module fpunit(p,co,clk,a,b);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
wire c1,c2,c3,c4;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [255:0] v1;
wire [256:0] v2,w1,w2;
parallelreg a1(
	.din	(256'b0),
	.clk	(clk),
	.rst	(1'b1),
	.dout	(s1)
);
parallelreg a2(
	.din	(256'b0),
	.clk	(clk),
	.rst	(1'b1),
	.dout	(s2)
);
flp a4(
	.u		(u),
	.v		(v1)
);
notb a5(
	.a		(s2),
	.y		(s3)
);
muxb a6(
	.a		(s1),
	.b		(s3),
	.s		(co),
	.y		(s4)
);
bitadd a7(
	.a		(s1),
	.b		(s4),
	.cin	(co),
	.c		(v2)
);
notg a8(
	.a		(co),
	.b		(c3)
);
notb a9(
	.a		(p),
	.y		(s5)
);
muxb a10(
	.a		(p),
	.b		(s5),
	.s		(c3),
	.y		(s6)
);
bitadd a12(
	.a		(v1),
	.b		(s6),
	.cin	(1'b1),
	.c		(w1)
);
bitadd a13(
	.a		(v2[255:0]),
	.b		(s6),
	.cin	(c3),
	.c		(w2)
);
org a14(
	.a		(w1[256]),
	.b		(v1[255]),
	.c		(c1)
);
org a15(
	.a		(w2[256]),
	.b		(v2[256]),
	.c		(c4)
);
muxg a16(
	.a		(v2[255]),
	.b		(c4),
	.s		(c3),
	.y		(c2)
);
muxb a17(
	.a		(w1[255:0]),
	.b		(v1[255:0]),
	.s		(c1),
	.y		(t1)
);
muxb a18(
	.a		(w2[255:0]),
	.b		(v2[255:0]),
	.s		(c2),
	.y		(t2)
);
parallelreg a21(
	.din	(a),
	.clk	(clk),
	.rst	(1'b0),
	.dout	(s1)
);
parallelreg a22(
	.din	(b),
	.clk	(clk),
	.rst	(1'b0),
	.dout	(s2)
);
generate
genvar i;
for(i=0;i<256;i=i+1)
begin: ABC
muxb a3(
	.a		(s1),
	.b		(s2),
	.s		(b[i]),
	.y		(u)
);
muxb a19(
	.a		(t1),
	.b		(t2),
	.s		(b[i]),
	.y		(a)
);
muxb a20(
	.a		(t2),
	.b		(t1),
	.s		(b[i]),
	.y		(b)
);
end
endgenerate
endmodule
i got this error
ERROR:Xst:880 - "flp.v" line 30: Cannot mix blocking and non blocking assignments on signal <v>.
when i simulate it using modelsim i got dis error
# ERROR: fpunit.v(109): near "i": expecting: '('
# ERROR: fpunit.v(130): near "end":syntax error
# ERROR: C:/Modeltech_5.5e/win32pe/vlog failed.
plz help me to solve it
Also notg is single bit not gate and notb is 256 bit not gate
 

genvar should be declared before generate.
why don't you look at some verilog examples ?
 
aruipksni said:
genvar should be declared before generate.
why don't you look at some verilog examples ?
Click to expand...
System Verilog allows for local genvar, but in Shyam Joe's case he's using Modelsom 5.5e which won't support any System Verilog constructs. So yes he has to place the genvar before the generate.

Shyam Joe, What is in the module flp.v? Please post the code for that module (please use syntax=verilog & /syntax tags so I don't have to count lines). Your issue with the mixing blocking and non-blocking statements is in that module.

On another subject, you don't need to have notb and notg modules you can parameterized the width of the NOT gate. Then set the parameter appropriately for the 1-bit and the 256-bit NOT gates. Do a search for "verilog parameter" and you should get some good examples of how to do this.

I'd still like to understand if this a school project (because I can't believe that anyone would willingly code something seemingly simple with all these instantiated modules )

Regards
 
aruipksni & ads-ee thanks for helping me.
flp is actually a left shifter,here is the code
Code Verilog - [expand]
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module flp(v,u);
input [255:0] u;
output reg [255:0] v;
integer i;
always @ (u)
begin
v[0]=u[255];
for(i=1;i<=255;i=i+1)
begin
v[i]<=u[i-1];
end
end
endmodule

It is not school project. i was instructed to do as such as given in the block dig attached
 

Attachments

  • block dig.doc
    198.5 KB · Views: 116

Shyam Joe said: 
Code Verilog - [expand]
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module flp(v,u);
input [255:0] u;
output reg [255:0] v;
integer i;
always @ (u)
begin
v[0]=u[255];
for(i=1;i<=255;i=i+1)
begin
v[i]<=u[i-1];
end
end
endmodule
Click to expand...
This looks like a single bit rotate to the left. You could have coded it simply as.
Code Verilog - [expand]
1

assign v = {u[254:0], u[255]);


back to your code, change the assignment v <= u[i-1]; to a non-blocking assignment v = u[i-1];
Shyam Joe said:
It is not school project. i was instructed to do as such as given in the block dig attached
Click to expand...
I'm guessing that the dotted lines around the functional blocks were your defined module boundaries? I getting the feeling that you're developing an ASIC with antiquated tools (given the Modelsim 5.5e) and the tools aren't capable of synthesizing more than a 1000 or so gates. So doing more than simple shifts, NOT gates, 2 input muxes is too much for it to handle. :-(

Regards
 
Last edited:

FYI, Modelsim 5.5e is 12 years old and was the last version to support Windows 95. Is that why you are using it? What hardware are you targeting that still supports that?
 

Is there any possible way to simulate my coding in Modelsim 5.5e itself??
 

Is there any possible way to simulate my coding in Modelsim 5.5e itself??
Click to expand...
Why not, all reports are about basic Verilog syntax problems, nothing related to Modelsim versions.

I assume it's a pure simulation respectively algorithm design project, not related to real hardware implementation, otherwise the question of available hardware libraries for V5.5e would have attracted attention before. But you can switch to a newer version any time.
 

Actually the problem with this piece of coding only

Code: 
genvar i;
generate
for(i=0;i<256;i=i+1)
begin: ABC
muxb a3(
	.a		(s1),
	.b		(s2),
	.s		(b[i]),
	.y		(u)
);
muxb a19(
	.a		(t1),
	.b		(t2),
	.s		(b[i]),
	.y		(a)
);
muxb a20(
	.a		(t2),
	.b		(t1),
	.s		(b[i]),
	.y		(b)
);
end
endgenerate
When i synthesize it using xilinx it shows no error. but when i simulate in modelsim 5.5 it shows dis error
# ERROR: fpunit.v(108): near ";": expecting: '('
# ERROR: fpunit.v(130): near "end":syntax error

these lines are shown as errors
genvar i;
end

when i simulate the other piece of code after deleting the entire generate block i got the output.
also when i simulate the generate block separately it shows the same error.

where is the problem actually??
in coding or in the version of Modelsim i'm using

anybody plz help me to solve it. and please rewrite the coding if possible
 

Quick hints:

- use syntax tags like ads-ee did above. That way we can find line numbers.
- provide testbench code.

That aside, put the genvar statement before the generate.
 

ModelSim 5.5 is not fully supporting Verilog 2001. I'm not sure regarding the generate construct. I started with ModelSim 6.x, it has full Verilog 2001 support.

But ModelSim comes with pretty much of documentation, how about reviewing the language support chapters?
 

I have a vague recollection that the Modelsim 5.x series didn't support genvar keyword. I think you need to use integer, but I don't guarantee that will work.

Regards
 

Hi friends i used modelsim 6.3 & i got output
Nw i started to code the next module. The coding is as follows
Code Verilog - [expand]
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module mulsubadd(clk,c,a0,a1,a2,b0,b1,b2,t1,t2,t3,p,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11);
input [255:0] p;
input clk;
input c,c1,c5,c6,c7,c8,c9,c10,c11;
input [1:0] c2,c3,c4;
input [255:0] a0,a1,a2,b0,b1,b2;
output [255:0] t1,t2,t3;
wire [255:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14;
parallelreg reg_1(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c7),
    .dout   (w1)
);
parallelreg reg_2(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c8),
    .dout   (w2)
);
parallelreg a3(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c10),
    .dout   (w3)
);
parallelreg a4(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c11),
    .dout   (w4)
);
muxb a5(
    .a      (a0),
    .b      (w1),
    .s      (c1),
    .y      (w5)
);
muxc a6(
    .a      (a1),
    .b      (b0),
    .c      (w2),
    .d      (256'b0),
    .s      (c2),
    .y      (w6)
);
fpunit a7(
    .clk    (clk),
    .co (c),
    .p      (p),
    .a      (w5),
    .b      (w6),
    .t      (w11)
);
muxc a8(
    .a      (b0),
    .b      (a1),
    .c      (w1),
    .d      (w3),
    .s      (c3),
    .y      (w7)
);
muxc a9(
    .a      (b1),
    .b      (w2),
    .c      (w4),
    .d      (256'b0),
    .s      (c4),
    .y      (w8)
);
fpunit a10(
    .clk    (clk),
    .co (c),
    .p      (p),
    .a      (w7),
    .b      (w8),
    .t      (w12)
);
muxb a11(
    .a      (w3),
    .b      (a2),
    .s      (c5),
    .y      (w9)
);
muxb a12(
    .a      (w4),
    .b      (b2),
    .s      (c6),
    .y      (w10)
);
fpunit a13(
    .clk    (clk),
    .co (c),
    .p      (p),
    .a      (w9),
    .b      (w10),
    .t      (w13)
);
muxb a14(
    .a      (w11),
    .b      (w13),
    .s      (c9),
    .y      (w14)
);
parallelreg a15(
    .din    (w11),
    .clk    (clk),
    .rst    (c7),
    .dout   (w1)
);
parallelreg a16(
    .din    (w12),
    .clk    (clk),
    .rst    (c8),
    .dout   (w2)
);
parallelreg a17(
    .din    (w14),
    .clk    (clk),
    .rst    (c10),
    .dout   (w3)
);
parallelreg a18(
    .din    (w12),
    .clk    (clk),
    .rst    (c11),
    .dout   (w4)
);
assign t1=w11;
assign t2=w12;
assign t3=w13;
endmodule

the submodules are
fpunit:
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module fpunit(p,co,clk,a,b,t);
input [255:0] p;
input co;
input clk;
inout [255:0] a,b;
output [255:0] t;
wire c1,c2,c3,c4,v2c,w1c,w2c;
wire [255:0] t1,t2,u,s1,s2,s3,s4,s5,s6;
wire [255:0] v1,v2,w1,w2;
parallelreg a1(
    .din    (256'b0),
    .clk    (clk),
    .rst    (1'b1),
    .dout   (s1)
);
parallelreg a2(
    .din    (256'b0),
    .clk    (clk),
    .rst    (1'b1),
    .dout   (s2)
);
flp a4(
    .u      (u),
    .v      (v1)
);
notb a5(
    .a      (s2),
    .y      (s3)
);
muxb a6(
    .a      (s1),
    .b      (s3),
    .s      (co),
    .y      (s4)
);
add a7(
    .a      (s1),
    .b      (s4),
    .cin    (co),
    .v      (v2),
    .co (v2c)
);
notg a8(
    .a      (co),
    .b      (c3)
);
notb a9(
    .a      (p),
    .y      (s5)
);
muxb a10(
    .a      (p),
    .b      (s5),
    .s      (c3),
    .y      (s6)
);
add a12(
    .a      (v1),
    .b      (s6),
    .cin    (1'b1),
    .v      (w1),
    .co (w1c)
);
add a13(
    .a      (v2),
    .b      (s6),
    .cin    (c3),
    .v      (w2),
    .co (w2c)
);
org a14(
    .a      (w1c),
    .b      (v1[255]),
    .c      (c1)
);
org a15(
    .a      (w2c),
    .b      (v2c),
    .c      (c4)
);
muxg a16(
    .a      (v2c),
    .b      (c4),
    .s      (c3),
    .y      (c2)
);
muxb a17(
    .a      (w1),
    .b      (v1),
    .s      (c1),
    .y      (t1)
);
muxb a18(
    .a      (w2),
    .b      (v2),
    .s      (c2),
    .y      (t2)
);
parallelreg a21(
    .din    (a),
    .clk    (clk),
    .rst    (1'b0),
    .dout   (s1)
);
parallelreg a22(
    .din    (b),
    .clk    (clk),
    .rst    (1'b0),
    .dout   (s2)
);
genvar i;
generate
for(i=0;i<256;i=i+1)
begin: ABC
muxb a3(
    .a      (s1),
    .b      (s2),
    .s      (b[i]),
    .y      (u)
);
muxb a19(
    .a      (t1),
    .b      (t2),
    .s      (b[i]),
    .y      (a)
);
muxb a20(
    .a      (t2),
    .b      (t1),
    .s      (b[i]),
    .y      (b)
);
end
endgenerate
assign t=a-b;
endmodule

muxb:
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module muxb(a,b,s,y);
input [255:0] a,b;
input s;
output [255:0] y;
reg [255:0] y;
always @(a,b,s)
case(s)
1'b0: y=a;
1'b1: y=b;
endcase
endmodule

muxc:
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module muxc(a,b,c,d,s,y);
input [255:0] a,b,c,d;
input [1:0] s;
output [255:0] y;
reg [255:0] y;
always @(a,b,c,d,s)
case(s)
2'b00: y=a;
2'b01: y=b;
2'b10: y=c;
2'b11: y=d;
default: y=256'b0;
endcase
endmodule

parallelreg:
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module parallelreg(din,clk,rst,dout);
input [255:0] din;
input clk,rst;
output reg [255:0] dout;
wire [255:0] din;
wire clk,rst;
always @(posedge clk or negedge rst)
if(!rst)
begin
dout<=256'b0;
end
else
begin
dout<=din;
end
endmodule

i'm not getting the output. hw to solve it. i hav attached my module block dig & the output i got
 

Attachments

  • BLCK DIG.doc
    362 KB · Views: 103

Shyam Joe said:
Hi friends i used modelsim 6.3 & i got output
Nw i started to code the next module. The coding is as follows

i'm not getting the output. hw to solve it. i hav attached my module block dig & the output i got
Click to expand...

Shyam Joe,

I still can't get past the fact that you are being forced to code this design in multiple files, that in my opinion should be done in a single file. The block diagram you posted suggests a single file of well commented behavioral RTL. If this hierarchical architecture was handed down to you from your supervisor, then I'd question the design chops of said supervisor (could this be a case of being promoted to cover incompetence? ;-)).

e.g.
Code Verilog - [expand]
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module muxc(a,b,c,d,s,y);
input [255:0] a,b,c,d;
input [1:0] s;
output [255:0] y;
reg [255:0] y;
always @(a,b,c,d,s)
case(s)
2'b00: y=a;
2'b01: y=b;
2'b10: y=c;
2'b11: y=d;
default: y=256'b0;
endcase
endmodule

Here you have 14 lines of code and a module you now have to instantiate when you could have just used the code from always ... endcase

Code written like this is hardly maintainable and is a total bitch to work with or read. I'm sorry, but I'm not even going to make the attempt. The last job I worked on that had similar code...I threw the code away and wrote my own module that replaced all the ridiculous over partitioning of the design.

Good luck, you'll need it.

- - - Updated - - -

must have missed seeing this post...
mrflibble said:
Quick hints:
That aside, put the genvar statement before the generate.
Click to expand...

mrfibble,

you can place the genvar after the generate and it will be local to that generate. I think this got introduced in SV. I know Modelsim 10.x, Altera, and Xilinx all support this syntax.
 
Reactions: FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
ads-ee said:
you can place the genvar after the generate and it will be local to that generate. I think this got introduced in SV. I know Modelsim 10.x, Altera, and Xilinx all support this syntax.
Click to expand...

Thanks, that good to know! I recall running into some trouble when I had it the other way around. Incidentally that was on Xilinx, on a fairly old version of ISE. Don't precisely remember the version, but I do remember that sticking to the above plan of genvar first and then generate magically solved it.

As an aside, can you think of a case where it would be a better practice to have the genvar locally to the generate? Not in defense of my out-dated practice, but more out of general interest. What would be a good use for it? Although maybe looking at it from an OO perspective I can see it. But usually when mucking about with verilog my OO sense goes out the window because plain verilog-2005 + OO == wishful thinking
 

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