i got error in the generate statement help me to rectify it

[Shyam Joe]

Hi friends i changed the code lyk dis

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Code Verilog - [expand]
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module mulsubadd(clk,a0,a1,a2,b0,b1,b2,t1,t2,t3,p,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11);
input [255:0] p;
input clk;
input c1,c5,c6,c7,c8,c9,c10,c11;
input [1:0] c2,c3,c4;
input [255:0] a0,a1,a2,b0,b1,b2;
output [255:0] t1,t2,t3;
wire [255:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14;
parallelreg reg_1(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c7),
    .dout   (w1)
);
parallelreg reg_2(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c8),
    .dout   (w2)
);
parallelreg a3(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c10),
    .dout   (w3)
);
parallelreg a4(
    .din    (256'b0),
    .clk    (clk),
    .rst    (c11),
    .dout   (w4)
);
muxb a5(
    .a      (a0),
    .b      (w1),
    .s      (c1),
    .y      (w5)
);
muxc a6(
    .a      (a1),
    .b      (b0),
    .c      (w2),
    .d      (256'b0),
    .s      (c2),
    .y      (w6)
);
fpadd a7(
    .p      (p),
    .a      (w5),
    .b      (w6),
    .t      (w11)
);
muxc a8(
    .a      (b0),
    .b      (a1),
    .c      (w1),
    .d      (w3),
    .s      (c3),
    .y      (w7)
);
muxc a9(
    .a      (b1),
    .b      (w2),
    .c      (w4),
    .d      (256'b0),
    .s      (c4),
    .y      (w8)
);
fpadd a10(
    .p      (p),
    .a      (w7),
    .b      (w8),
    .t      (w12)
);
muxb a11(
    .a      (w3),
    .b      (a2),
    .s      (c5),
    .y      (w9)
);
muxb a12(
    .a      (w4),
    .b      (b2),
    .s      (c6),
    .y      (w10)
);
fpadd a13(
    .p      (p),
    .a      (w9),
    .b      (w10),
    .t      (w13)
);
muxb a14(
    .a      (w11),
    .b      (w13),
    .s      (c9),
    .y      (w14)
);
parallelreg a15(
    .din    (w11),
    .clk    (clk),
    .rst    (c7),
    .dout   (w1)
);
parallelreg a16(
    .din    (w12),
    .clk    (clk),
    .rst    (c8),
    .dout   (w2)
);
parallelreg a17(
    .din    (w14),
    .clk    (clk),
    .rst    (c10),
    .dout   (w3)
);
parallelreg a18(
    .din    (w12),
    .clk    (clk),
    .rst    (c11),
    .dout   (w4)
);
assign t1=w11;
assign t2=w12;
assign t3=w13;
endmodule
[/syntax=verilog]
the sub module fpadd is
[syntax=verilog]
module fpadd(p,a,b,t);
input [255:0] p,a,b;
output [255:0] t;
reg [255:0] su1,su2;
reg c1,c2;
reg [255:0] v1,t1,t2,u;
reg [255:0] v2,w1,w2;
integer i;
parameter s=1;
initial
begin
for(i=0;i<256;i=i+1)
begin
if(b[i])
u=a;
else
u=256'b0;
v1=u<<s;
v2=a+b;
w1=v1+(~p)+1;
w2=v2+(~p)+1;
c1=w1[3] | v1[3];
c2=w2[3] | v2[3];
if(c1)
t1=w1;
else
t1=v1;
if(c2)
t2=w2;
else
t2=v2;
if(b[i])
begin
su1=t1;
su2=t2;
end
else
begin
su1=t2;
su2=t1;
end
end
end
assign t=su1-su2;
endmodule
[/syntax=verilog]
when i simulate the code i'm not getting o/p for the signals w1,w2,w11,w12,w13,w14. I think the problem is with fpadd subunit only.
Also when i synthesize i get the following warnings. help me to solve.
Analyzing module <fpadd>.
    s = 32'sb00000000000000000000000000000001
WARNING:Xst:2320 - "fpadd.v" line 15: Value for signal u in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 18: Value for signal v1 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 19: Value for signal v2 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 20: Value for signal w1 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 21: Value for signal w2 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 22: Value for signal c1 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 23: Value for signal c2 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 25: Value for signal t1 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 29: Value for signal t2 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 34: Value for signal su1 in initial block is not constant. The initialization will be ignored.
WARNING:Xst:2320 - "fpadd.v" line 35: Value for signal su2 in initial block is not constant. The initialization will be ignored.
Module <fpadd> is correct for synthesis.
Synthesizing Unit <fpadd>.
    Related source file is "fpadd.v".
WARNING:Xst:1872 - Variable <i> is used but never assigned.
WARNING:Xst:1780 - Signal <u> is never used or assigned.
WARNING:Xst:1780 - Signal <c1> is never used or assigned.
WARNING:Xst:1780 - Signal <c2> is never used or assigned.
WARNING:Xst:1780 - Signal <t1> is never used or assigned.
WARNING:Xst:1780 - Signal <t2> is never used or assigned.
WARNING:Xst:1780 - Signal <v1> is never used or assigned.
WARNING:Xst:1780 - Signal <v2> is never used or assigned.
WARNING:Xst:1780 - Signal <w1> is never used or assigned.
WARNING:Xst:1780 - Signal <w2> is never used or assigned.
WARNING:Xst:653 - Signal <su1> is used but never assigned. Tied to value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.
WARNING:Xst:653 - Signal <su2> is used but never assigned. Tied to value 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.

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[FvM]

1. Your code tags are obviously invalid.
2. The warnings are rather self explanatory, I think. All of your fpadd code is placed in the initial block, but none of it should be there.

The problem is apparently about understanding basic Verilog semantic.

 

[mrflibble]

At the end you only have to use [/syntax] to end the syntax block.

As for warnings like "Value for signal v1 in initial block is not constant. The initialization will be ignored.", those are fairly understandable I would think, and easy enough to fix. Somewhere in the initial block of your testbench that you did not include in your post you assign a non-constant value. The simulator is unable to evaluate what value it should put there, so it ignores the initialization. And even tells you about it so you can fix things.

MMmmh, just realized I was being far more generous than FvM. I was assuming some sort of small mistake in the initial block. If however you have put your entire fpadd in the initial block, uuuuhm, yes. If you did that, get some coffee, and get a good verilog book.

In any event, next time include your testbench code as well. Oh, and tip: you can use the "Preview Post" button so you can see if your syntax tags are working properly.