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How to reduce mistach in CMOS analog IC design?

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leonken

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How to reduce mistach in CMOS analog IC deisgn ,especially for current source, bandgap voltage reference design?
Thank you
 

Some basic rules:

1. Increas the size of the devices to be matched
2. Use simmetric layout
3. Replicate the same geometry using series/parallel connection to achieve the wanted size.


Bye
 

hi
use can pcell establish the same geometry . you can look at on "ic mask design" book!
 

Refer to Razavi and Martin's classic books.
 

mylihua said:
hi
use can pcell establish the same geometry . you can look at on "ic mask design" book!

Hi
Where I can find this book?
I don't find it on this site....can upload this book for us?
 

Another:

Use dummy device
 

For current source,use cascode architecture, or use source series resistor to improve matching.
 

sunking said:
Another:

Use dummy device

Where I can find some documents about the dummy device application?
Thank you!
 

CDRCDR said:
For current source,use cascode architecture, or use source series resistor to improve matching.
Can you give me some links about such topic?
Thank you
 

I have a questions: What condition for the matching parameters Avt and Ak based on? Is it based on just two same structure spaced closed to each other (without interdigit), or stands Avt for interdigit or common-centroid one? For example, if datasheet say Avt = 1% um, will common-centroid layout improves this level of matching?
 

Utilize degen resistor to help match, passive devices should have better
matching performance than active device, due to simpler process.
 

"The Art of Analog Layout" discusses much about device matching. This book can be download from this site.
 

Yes, "The Art of Analog Layout" is really good for understanding the basics of matching. Here is the link:
 

common centriod structures, see to 'The art of analog design'
 

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