How to protect the IP in an FPGA design?

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What do You mean:
"Also, you can spend 2 pins (in + out) of your FPGA for test traffic."
Please give more details.
 

Hello spktu,

I think that YUV means that you can use two pins for the communication between the CPLD and the FPGA for testing the "key".

Bye,
cube007
 

How do You estimate AVR ATMEGA128 as security CPLD?

How do You estimate AVR ATMEGA128 serving as that kind of CPLD ( configuration loader + security ) for @ltera Cyclone ?
 

U can use FPGA + PLD to protect your design
 

spktu said:
What do You mean:
"Also, you can spend 2 pins (in + out) of your FPGA for test traffic."
Please give more details.
Click to expand...
I mean, you can use 2 pins of your FPGA for checking a presence of hidden connection on PCB. Thus, your PCB can act as a "key".
Anyway, routing PCB you can easy put a secret wire into internal layer.
 

I do not quite agree. The vertical fuses used by Actel makes it virtually impossible to 'see' the content of this kind of FPGAs. Beside they are radiation hardened, therefore X-ray analysys does not work.

Their Flash based FPGA's takes away the burden of prototyping and you can (if really required) transfer your design to a fuse base one.

Cheers.


tahiti said:
This is not true. A chip, especially fuse based devices, can be reingineered, if someone is willing to invest a significant amount of money.

And, as far as I know 3DES can be cracked, if you have extremely large computing power.

tahiti
Click to expand...
 

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