How to protect the IP in an FPGA design?

[spktu]

What do You mean:
"Also, you can spend 2 pins (in + out) of your FPGA for test traffic."
Please give more details.

 

[cube007]

Hello spktu,

I think that YUV means that you can use two pins for the communication between the CPLD and the FPGA for testing the "key".

Bye,
cube007

 

[spktu]

How do You estimate AVR ATMEGA128 as security CPLD?

How do You estimate AVR ATMEGA128 serving as that kind of CPLD ( configuration loader + security ) for @ltera Cyclone ?

 

[james_rabbit]

U can use FPGA + PLD to protect your design

 

[YUV]

What do You mean:
"Also, you can spend 2 pins (in + out) of your FPGA for test traffic."
Please give more details.

I mean, you can use 2 pins of your FPGA for checking a presence of hidden connection on PCB. Thus, your PCB can act as a "key".
Anyway, routing PCB you can easy put a secret wire into internal layer.

 

[henrik2000]

I do not quite agree. The vertical fuses used by Actel makes it virtually impossible to 'see' the content of this kind of FPGAs. Beside they are radiation hardened, therefore X-ray analysys does not work.

Their Flash based FPGA's takes away the burden of prototyping and you can (if really required) transfer your design to a fuse base one.

Cheers.

This is not true. A chip, especially fuse based devices, can be reingineered, if someone is willing to invest a significant amount of money.

And, as far as I know 3DES can be cracked, if you have extremely large computing power.

tahiti