How to improve the bandgap's high frequency PSRR?

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Explain about which one?
Also mention about who you are asking to..
Thanks,
Saro
 


sorry, i don't express it clearly.
saro_k_82, may you explainn the idea in detail, how to include a third arm in the existing amp and have two second stage? better with drawing, thanks!
 

The cap couples the supply noise directly to the gate of the pmos transistors., which means that at high frequency the gate and source move together -> PMOS current is unaffected. If you had a cap to ground, PSRR will be worse as the gate will not move with the supply and you allow supply noise in to the circuit and depend only on the amp's gain to reject it. As amp loses it's gain after the first pole, if you are able to roll off the contribution of supply noise, you would improve PSRR!!
If you are ok with offsets it is great., but did you check reversing the offset (I don't know the polarity of the included offset) and check at other spots as well?
To find out the expected random mismatch term, you need to look in to the pdk for the AVT number.[/quote]


ok, good! i agree if for Pmos, you put a cap between gate and source will improve PSRR at high frequency. Basically if short at high frequency , the Vsg become zero and the transistor is off.

how about for Nmos, can i put a cap between gate and source?

so that it will short at high frequency and increase PSRR? Will it help?
 

I have attached the images. It is only to instruct about the architecture., so don't get carried away with the device sizes. I din't include the startup too..
 


Yes that will help for PSRR but may not be good in general. As long as you keep the low impedances low and high impedances high at high frequencies your PSRR will be better. But in this circuit doing so will hamper the stability of the loop. Caps need to be added for 3 purposes., Stability, PSRR and noise. Including them at different places give you different bargains for the three., but including the cap the way that I have indicated will improve all three....again just for this circuit.
 


just to confirm, If stability not the issue, then put a cap between gate and source for nmos will help Psrr at high frequency?
 

surianova said:
just to confirm, If stability not the issue, then put a cap between gate and source for nmos will help Psrr at high frequency?
Click to expand...

YES
 

Add a cap between the output of opamp and vdd improves the psrr.
 

to improve PSRR+ (supply rejection to the positive supply VDD), we want the impedance from the output node to VDD to be high.

If you add a capacitor between the gate and source of the pmos, wouldnt that turn the pmos off at high frequency? Doesnt that make the PSRR at high frequency worse because your circuit would be off? :?
 


yes, we want to Pmos to be off at high frequecny, so that the noise from VDD won't be able to amplifly to the output.
 

surianova said:
yes, we want to Pmos to be off at high frequecny, so that the noise from VDD won't be able to amplifly to the output.
Click to expand...
How does the BGR circuit function if the pmos is off?
 

ytliang said:
How does the BGR circuit function if the pmos is off?
Click to expand...

Simple answer is that BGR's signals are close to dc., whereas the noise that we want to attenuate are high frequency.

When he says that the PMOS is off, he onlt means that there is an ac short between it's gate and source so the PMOS is blind towards high frequency supply noise.

Miller capacitor does not turn the transistor OFF. It just shorts the drain and gate. It drops the impedance of a high impedance node and it results in poor Supply rejection.

You are right in saying that the impedance from the supply to the out node be high (This is true here and not in general., try speaking of GND rejection with cap connected from OUT to GND). The cap is not connected to the output node., by connecting the cap there the output is coupled more to ground than to supply which improves PSRR.
 

Thanks, looks like I was confused with small signal and dc.

Regarding the GND rejection (PSRR- in some text books), Could you please elaborate more on how a high impedance from OUT to GND does not imply good GND rejection?
 

It depends on whether you have your output referred to GND or VDD. The one to which it is referred to should see low impedance and high impedance to the other for high noise rejection.
In this circuit, if you have high impedance from OUT to GND and feed the reference to an DAC., the OUT won't move when the GND does (But the DAC's GND has moved) which will amount to large errors at the output of DAC.
 


ipsc: What's the trick to fix the 1st problem alone?


Dear saro_k_82,
I compiled, above, your comments on the Stability and/or Startup problems, due to Mismatches, associated with the Architecture under discussion & one of the solutions proposed by you for the same. I took the liberty to make small changes in them for continuity, which I marked bold. I hope this is agreeable to you.


/****************************************************************
Before describing my problem that brought me here, for which I need your help, let me first share, some of my views on above discussion:

I completely agree with all your comments, above, on the problems with the current Architecture. I am also fine with your proposed 'Two Amplifier' based Architecture which solves the problem completely but at some Area & Power overhead.

To reduce that Power & Area overhead a bit, you proposed a wonderful & out of the box idea that has a third arm in the existing diff-pair and have two second stages.
=>=>=>=>
If I understand correctly, what this achieves is: It removes the Area & Power overhead of one more Diff-Pair & Area overhead of one more compensation Cap. Am I correct? Or are there any additional benefits with this?

But on the flip side, this will have more systematic offset & may be more Random offset even because Opamp is biased by Q0 or Q1’s current not by 'Q2' branch's current & hence sizes of M14-M15 & M11-M13 might be different in Practical case.

May I have your comments on this? Also is there any technique to mitigate this problem?

One more thing, that isn't completely clear to me is the logic behind craving out the Third diff-pair branch out of Opamp's overall -ve Input & not +ve Input. I think this will weaken -ve feedback & hence stability. What's your take?

BTW, what should be the ideal ratio between currents of 1st, 2nd & 3rd branch of diff-pair?

You mentioned that,
saro_k_82 said:
Well this is just one of the many possibilities to get out of this problem.
Click to expand...
Could you please post other ways as well, if it's possible? If you can't publish them all, it would be great, if you can at least guide me to the Literature on them?
<=<=<=<=


========
You also mentioned that:
saro_k_82 said:
Even though the circuit finding a stable operating point that is different from the ‘2’ expected operating regions can be abated with a strong startup circuit, it cannot be avoided and it costs the design in other parameters.
Click to expand...

Can you please elaborate this point a bit more? -- May be with a drawing of that strong start-up circuit & description of the parameters it will cost.
========
****************************************************************/



/****************************************************************
Now coming to my problem:

In the Design, on which I am working now, due to VBE variation & VT issues I can't use VBE directly. I have to use divided down value of VBE as I/P to a PMOS OTA. (Note: I can't use NMOS I/P one even). This means - I must have to use ‘Resistor in parallel to BJT’ Architecture.

Do you have any idea on solving above problems with this kind of Architecture i.e. solving above problem while retaining Resistors in parallel to BJT?
****************************************************************/

with warm regards
ipsc
 

The negative feedback dominates only because the impedance seen on the resistor arm is higher than the diode-only arm. If you find a way to make sure that this will be the case even after you insert the shunt resistors, you'll be fine. The trick is to sample the shunt resistor current with low impedance and drawing exactly the same current with high impedance on the other side. i.e Add an arm with resistor and a mos diode in series in parallel to the diode-only arm. Use the VGS generated and mirror 1:1 the current in the other arm with the same resistor. This way you'll get the same temperature characteristic (neglecting the mos tempco error., which will not be negligible., but this is just the idea at the first level) while maintaining or improving the relative impedance levels at both the terminals.
There are a few caveats about this implementation as well. The opamp could find a stable operating point where both the arms are dominated by the MOS voltages where the pn diodes are carrying very low current., which can be avoided by turning on the shunt elements after the bandgap stabilizes with the pn diode voltages. Other advanced implementations of the same idea can avoid this.


It reduces the area, power and random mismatch., but not the compensation cap. Well in principle you can work with one compensation cap for the two loops but it will either call for a very huge cap or complex network. With this simple scheme, you need two caps and they can be moscaps.


Q2 is of the same size as Q0 and as the loop forces the same voltage on Q2, the current in it will be the same as Q0, but the current in R1 will increase the current in M2 compared to that in M0, M1 ., etc. This wont cause systematic offset as long as you understand this and size M2 as an array of transistors of M1's size. If M1 were carrying 25uA and M2 carries 100uA, M2 has to 4 transistors M1 transistors in parallel. I know this is not possible always, but you can reduce the systematic error by a great deal this way. If you want to reduce furthur, you can incude a nmos diode in the S1 arm and use that VGS to another matched nmos transistor in the S2 arm. This is basically cascoding to reduce the difference in VDS that M11 and M13 sees.

ipsc said:
One more thing, that isn't completely clear to me is the logic behind craving out the Third diff-pair branch out of Opamp's overall -ve Input & not +ve Input. I think this will weaken -ve feedback & hence stability. What's your take?
ipsc
Click to expand...

In the present architecture diagram that I had uploaded, The diode-only arm is loaded with the input cap of the opamp and the other arm is left free, which reduces the impedance level of that arm around the loop's UGB which is good for stability.
After all the nodes of the first loop are stabilized, it hardly matters where you are going to tap (ofcourse the input cap matters)
Also if I had tapped it from +, I need a 3 stage amp in order to use this architecture.

All the 3 arms of the first stage should have same currents (1:1:1).

ipsc said:
Could you please post other ways as well, if it's possible? If you can't publish them all, it would be great, if you can at least guide me to the Literature on them?
ipsc
Click to expand...
There is a huge chunk of literature about alternative methods., it would be hard to point to one. If you want to keep it simple, just have the core PTAT generator with one amp and drop the PTAT current in two separate branches to a resistor and a diode. Insert a balancing resistor between the two branches to get the bandgap voltage.

ipsc said:
Can you please elaborate this point a bit more? -- May be with a drawing of that strong start-up circuit & description of the parameters it will cost.
ipsc
Click to expand...

It is already a long reply and I'm lazy to do it now. In short, stronger the startup circuit, there may be two problems.
i. The startup loop works (atleast partly) even after the loop is completely up and then put off, which might cause a huge glitch in the loop initiating the startup loop again. So the startup circuit can be on-off always.
ii. The key transistor that is used to provide the startup current will not be completely off and would leak a lot affecting stability, curvature and supply rejection (this is often overlooked).

If you have to use the shunt resistor, you could use high enough resistors so that all these problems are avoided.
 

Dear saro_k_82,

Firstly thanks a lot for such a detailed reply. And pardon me for the delay in my reply.

Yeah, this will be a risky Architecture.

Thanks for the clarification. The caps will be on F1 & F2 nets to the GND, right?

I am afraid.... this might be somewhat workable only if the design is for a single process corner because even with temperature M1 current varies a lot while M2 current is relatively constant.

saro_k_82 said:
If you want to reduce furthur, you can incude a nmos diode in the S1 arm and use that VGS to another matched nmos transistor in the S2 arm. This is basically cascoding to reduce the difference in VDS that M11 and M13 sees.
Click to expand...
I am afraid.... Even this might help only a bit if the design spreads in several process corners.

Actually I was talking about single opamp based architecture (1st diagram) not the 2nd one. Any way, I was thinking that the ratio will be 2:1:1. If it's 1:1:1 probably that should be fine.

saro_k_82 said:
There is a huge chunk of literature about alternative methods., it would be hard to point to one.
Click to expand...
I know there is huge literature. But it would be great if you can point me to one good paper/book from where I can proceed further (i.e. probably a good paper/book that has one or more references to other good ones.)

saro_k_82 said:
If you want to keep it simple, just have the core PTAT generator with one amp and drop the PTAT current in two separate branches to a resistor and a diode. Insert a balancing resistor between the two branches to get the bandgap voltage.
Click to expand...
Do you mean something like the attached image?

Pardon me; I can’t understand how did it will give me the bandgap voltage. Can you please explain its function a bit or point to its source?

saro_k_82 said:
If you have to use the shunt resistor, you could use high enough resistors so that all these problems are avoided.
Click to expand...
If I correctly understand the problems with current architecture, this might need too high resistors of the order Mega ohms. Any way, let me see if it’s workable in my area limitations.

Thank You for your help.

With Warm Regards
ipsc

PS: on a side note, the images you have attached are directly shown in the message, while mine are not. May I know, what's the trick for it? Because it will be lot more convienient to the people to follow.
 

ipsc said:
Thanks for the clarification. The caps will be on F1 & F2 nets to the GND, right?
Click to expand...
Yes
ipsc said:
I am afraid.... this might be somewhat workable only if the design is for a single process corner because even with temperature M1 current varies a lot while M2 current is relatively constant.
Click to expand...
You are right. The process variation will be handled well, but there will be temperature induced systematic offset. This can only be reduced by maximizing the gm of M11, M13, M12, M4, M3 and the three input transistors and minimizing the gm of M14, M15, etc. Moreover if the input transistors are well in to weak inversion, the offset will look like a diode induced CTAT (In BJT process, designers purposely invite offset as it is again dVBE and use it as signal) which can be corrected and the systematic error will not cause any trouble.
ipsc said:
Pardon me; I can’t understand how did it will give me the bandgap voltage. Can you please explain its function a bit or point to its source?
Click to expand...
The current form P2 and P3 are PTAT. The diode will give a CTAT voltage and R1 will show a PTAT voltage(without R2). The R2 resistor sends in just the amount of CTAT current to make the voltage at R1 independent of temperature.

About the images., I guess it is only because I have uploaded jpeg and you have uploaded png.

Best wishes,
Saro
 
saro_k_82 said:
I have attached the images. It is only to instruct about the architecture., so don't get carried away with the device sizes. I din't include the startup too..
Click to expand...

Can someone explain how this is zero TC? I get VBG= Vt ln 7 + Vbe
 

snafflekid said:
Can someone explain how this is zero TC? I get VBG= Vt ln 7 + Vbe
Click to expand...

Should be Vt ln 7 + Vbe*R2/R1

Vt ln(7) is PTAT and Vbe is CTAT isnt it. So adding them should give you zero TC at some current value. Of course one needs to tweak a bit to get the exact value as in any design.
 
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